18104556. PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME simplified abstract (Samsung Display Co., Ltd.)
Contents
PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME
Organization Name
Inventor(s)
KEUNWOO Kim of Seongnam-si (KR)
PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18104556 titled 'PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME
Simplified Explanation
The abstract describes a pixel circuit that consists of two transistors and polycrystalline silicon doped with different impurities.
- The first transistor has a gate terminal connected to a gate node and a first terminal with polycrystalline silicon doped with a first impurity. The first terminal is also connected to a first voltage. The second terminal of the first transistor also has polycrystalline silicon doped with the first impurity.
- The second transistor has a gate terminal connected to a first gate signal, a third terminal with polycrystalline silicon doped with a second impurity, and a fourth terminal with polycrystalline silicon doped with the second impurity.
Potential applications of this technology:
- Display technologies, such as LCD or OLED screens, where pixel circuits are used to control individual pixels.
- Image sensors, where pixel circuits are used to capture and process light signals.
Problems solved by this technology:
- Improved performance and functionality of pixel circuits by utilizing different impurities in the polycrystalline silicon, allowing for more precise control of the transistors.
- Reduction of noise and signal interference in pixel circuits, resulting in clearer and more accurate image or display quality.
Benefits of this technology:
- Enhanced image quality and resolution in displays or image sensors.
- Improved power efficiency and response time of pixel circuits.
- Increased flexibility and versatility in designing pixel circuits for various applications.
Original Abstract Submitted
A pixel circuit includes a first transistor a first gate terminal electrically connected to a gate node, a first terminal including polycrystalline silicon doped with a first impurity and electrically connected to a first voltage and a second terminal including polycrystalline silicon doped with the first impurity, and a second transistor a second gate terminal electrically connected to a first gate signal, a third terminal including polycrystalline silicon doped with a second impurity and electrically connected to the gate node and a fourth terminal including polycrystalline silicon doped with the second impurity.
