18104554. SEMICONDUCTOR DEVICE simplified abstract (KABUSHIKI KAISHA TOSHIBA)

SEMICONDUCTOR DEVICE

Organization Name

KABUSHIKI KAISHA TOSHIBA

Inventor(s)

Kyo Tanabiki of Himeji Hyogo (JP)

Yoshihiro Higashikawa of Tokyo (JP)

Hajime Takagi of Nonoichi Ishikawa (JP)

SEMICONDUCTOR DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18104554 titled 'SEMICONDUCTOR DEVICE

Simplified Explanation

The patent application describes a technology involving multiple chips on separate lead frames, each with source electrodes and terminals connected by conductors.

• First chip on a first lead frame:

   - Includes a first source electrode on a surface opposite to the first lead frame.
   - First source terminal located in a first direction from the first lead frame.
   - First gate terminal located in a second direction from the first source terminal.
   - First conductor contacts the first source electrode and the first source terminal via conductors.

• Second chip on a second lead frame:

   - Includes a second source electrode on a surface opposite to the second lead frame.
   - Second gate terminal located in a second direction from the first gate terminal.
   - Second source terminal located in the second direction from the second gate terminal.
   - Second conductor contacts the second source electrode and the second source terminal via conductors.

Potential Applications

This technology could be applied in the manufacturing of electronic devices such as integrated circuits, sensors, and microprocessors.

Problems Solved

This technology allows for efficient connection and communication between multiple chips on separate lead frames, improving overall performance and functionality.

Benefits

The technology enables enhanced functionality and connectivity in electronic devices, leading to improved efficiency and performance.

Potential Commercial Applications

The technology could be utilized in the production of advanced electronic devices for various industries, including telecommunications, automotive, and consumer electronics.

Possible Prior Art

Prior art in the field of semiconductor manufacturing and integrated circuits may exist, but specific examples are not provided in the patent application.

How does this technology impact the size of electronic devices?

This technology could potentially reduce the size of electronic devices by allowing for more compact and efficient chip placement and connectivity.

What are the potential cost implications of implementing this technology in electronic devices?

The use of this technology may lead to increased production costs initially, but could result in cost savings in the long run due to improved performance and efficiency.

Original Abstract Submitted

A first chip on a first lead frame includes a first source electrode on a surface opposite to the first lead frame. A first source terminal is located in a first direction from the first lead frame. A first gate terminal is located in a second direction from the first source terminal. A first conductor contacts the first source electrode and the first source terminal via conductors. A second chip on a second lead frame includes a second source electrode on a surface opposite to the second lead frame. A second gate terminal is located in a second direction from the first gate terminal. A second source terminal is located in the second direction from the second gate terminal. A second conductor contacts the second source electrode and the second source terminal via conductors.