18101254. SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOF
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18101254 titled 'SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOF
Simplified Explanation
The semiconductor device structure described in the abstract includes:
- Vertically stacked semiconductor layers over a substrate
- Source/drain features in contact with each semiconductor layer
- Inner spacers between adjacent semiconductor layers
- Gate electrode layer surrounding a portion of each semiconductor layer
- Gate dielectric layer between the semiconductor layer and gate electrode layer
- Gate spacer in contact with a portion of the gate dielectric layer
- First cap layer with portions in contact with the source/drain feature, gate spacer, and inner spacer
Potential applications of this technology:
- Advanced semiconductor devices
- High-performance electronic devices
- Integrated circuits
Problems solved by this technology:
- Improved performance and efficiency of semiconductor devices
- Enhanced functionality of electronic devices
- Better integration of components in integrated circuits
Benefits of this technology:
- Increased speed and reliability of electronic devices
- Higher density and scalability of integrated circuits
- Enhanced overall performance of semiconductor devices
Original Abstract Submitted
Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a plurality of semiconductor layers vertically stacked over a substrate, a source/drain feature in contact with each of the plurality of the semiconductor layers, an inner spacer disposed between two adjacent semiconductor layers, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a gate dielectric layer disposed between the semiconductor layer and the gate electrode layer, a gate spacer in contact with a portion of the gate dielectric layer. The semiconductor device structure further includes a first cap layer comprising a first portion disposed between and in contact with the source/drain feature and the gate spacer, and a second portion disposed between and in contact with gate spacer and the inner spacer.
