18100969. TEST CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME simplified abstract (SK hynix Inc.)
Contents
- 1 TEST CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 TEST CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
TEST CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
Organization Name
Inventor(s)
Suk Hwan Choi of Icheon-si Gyeonggi-do (KR)
TEST CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18100969 titled 'TEST CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
Simplified Explanation
The present technology includes a current mirror, a comparison circuit, and a test control circuit. The current mirror applies a test current generated by a test voltage to a selected word line and generates a copy current by copying the test current. The comparison circuit compares at least one reference current with the copy current to generate a comparison result signal. The test control circuit performs a first noise control mode that charges unselected word lines with electric charges and floats the unselected word lines in response to a test mode signal.
- Current mirror applies test current to selected word line
- Comparison circuit compares reference current with copy current
- Test control circuit charges unselected word lines with electric charges
Potential Applications
This technology could be applied in memory devices, such as flash memory or DRAM, to improve data retention and reduce noise interference.
Problems Solved
1. Improved data retention in memory devices 2. Reduced noise interference in memory operations
Benefits
1. Enhanced reliability of memory devices 2. Increased performance through noise control 3. Improved overall efficiency of memory operations
Potential Commercial Applications
Optimized Memory Noise Control Technology for Enhanced Data Retention
Possible Prior Art
There may be prior art related to current mirrors and noise control circuits in memory devices, but specific examples are not provided in this context.
Unanswered Questions
How does this technology compare to existing noise control methods in memory devices?
This article does not provide a direct comparison with existing noise control methods in memory devices. Further research or testing may be needed to evaluate the effectiveness of this technology in comparison to other methods.
What impact could this technology have on the overall performance of memory devices?
While the benefits of the technology are outlined, the specific impact on the overall performance of memory devices is not quantified. Additional studies or data analysis may be required to determine the extent of performance improvements.
Original Abstract Submitted
The present technology may include: a current mirror configured to apply a test current that is generated by a test voltage to a selected word line, among a plurality of word lines, and to generate a copy current by copying the test current; a comparison circuit configured to compare at least one reference current with the copy current to generate a comparison result signal; and a test control circuit configured to perform a first noise control mode that charges unselected word lines, among the plurality of word lines, with electric charges, in response to a test mode signal and floats the unselected word lines.
