18093932. CMOS TOP SOURCE/DRAIN REGION DOPING AND EPITAXIAL GROWTH FOR A VERTICAL FIELD EFFECT TRANSISTOR simplified abstract (International Business Machines Corporation)
Contents
CMOS TOP SOURCE/DRAIN REGION DOPING AND EPITAXIAL GROWTH FOR A VERTICAL FIELD EFFECT TRANSISTOR
Organization Name
International Business Machines Corporation
Inventor(s)
Heng Wu of Santa Clara CA (US)
Ruilong Xie of Niskayuna NY (US)
Jay William Strane of Warwick NY (US)
Hemanth Jagannathan of Niskayuna NY (US)
CMOS TOP SOURCE/DRAIN REGION DOPING AND EPITAXIAL GROWTH FOR A VERTICAL FIELD EFFECT TRANSISTOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 18093932 titled 'CMOS TOP SOURCE/DRAIN REGION DOPING AND EPITAXIAL GROWTH FOR A VERTICAL FIELD EFFECT TRANSISTOR
Simplified Explanation
The abstract describes a method for fabricating highly doped top source/drains in field effect transistors (FETs) with minimal lithography and etching processes. This method allows for the formation of FETs with increased functionality and reduced scaling.
- The method involves forming a p-type FET region and an n-type FET region in a semiconductor substrate.
- The process flow used in this method enables the fabrication of highly doped top source/drains.
- The method minimizes the need for lithography and etching processes, reducing the complexity and cost of fabrication.
- The resulting FETs have increased functionality, meaning they can perform more complex tasks.
- The method also allows for reduced scaling, which means the FETs can be made smaller while still maintaining their performance.
Potential Applications
This technology can have various applications in the field of semiconductor devices and integrated circuits. Some potential applications include:
- Microprocessors and CPUs: The highly doped top source/drains can enhance the performance and functionality of these key components in computing devices.
- Memory devices: The increased functionality of the FETs can improve the speed and capacity of memory devices such as RAM and flash memory.
- Communication devices: The reduced scaling capability can be beneficial for the fabrication of smaller and more efficient transistors used in wireless communication devices.
Problems Solved
The method described in the patent application solves several problems in the fabrication of FETs:
- Complex lithography and etching processes: By minimizing the need for these processes, the method simplifies the fabrication process and reduces manufacturing costs.
- Limited functionality: The highly doped top source/drains enable FETs to perform more complex tasks, enhancing their functionality.
- Scaling limitations: The method allows for reduced scaling, meaning FETs can be made smaller without sacrificing performance.
Benefits
The use of this method offers several benefits:
- Cost reduction: By minimizing the need for complex lithography and etching processes, the fabrication process becomes more cost-effective.
- Improved functionality: The highly doped top source/drains enable FETs to perform more complex tasks, expanding their range of applications.
- Size reduction: The ability to scale down FETs while maintaining performance allows for the creation of smaller and more efficient semiconductor devices.
Original Abstract Submitted
A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.
