18093560. MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
Organization Name
Inventor(s)
Jun Jin Kong of Yongin-si (KR)
Jin-Hoon Jang of Uiwang-si (KR)
MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18093560 titled 'MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
Simplified Explanation
The patent application describes a memory device that includes a memory cell array, an ECC engine, a row fail detector, and a flag generator.
- The memory cell array consists of memory cells arranged in multiple rows.
- The ECC engine is responsible for detecting errors in data read from the memory cell array, correcting the errors, and generating an error occurrence signal.
- The row fail detector identifies a fail row among the rows in the memory cell array and outputs the fail row address.
- The flag generator receives the read address, error occurrence signal, and fail row address to generate a decoding state flag and a fail row flag.
- The decoding state flag indicates whether an error is detected and whether it is corrected.
- The fail row flag indicates that the read row address is the fail row address.
Potential applications of this technology:
- Memory devices in computer systems, servers, and data centers.
- Solid-state drives (SSDs) and flash memory devices.
- Embedded systems and microcontrollers.
Problems solved by this technology:
- Detection and correction of errors in data read from memory cells.
- Identification of fail rows in the memory cell array.
- Efficient generation of decoding state and fail row flags.
Benefits of this technology:
- Improved data reliability and integrity.
- Enhanced error correction capabilities.
- Simplified error detection and correction process.
- Efficient identification of fail rows for troubleshooting and maintenance.
Original Abstract Submitted
A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
