18093473. SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
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SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME
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SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18093473 titled 'SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME
Simplified Explanation
The patent application describes a semiconductor memory device and a memory system. The device includes a memory cell array, refresh row address generators, a refresh selection signal generator, and a selector.
- The memory device performs normal and hammer refresh operations on a memory cell array block.
- The normal and hammer refresh row address generators generate row addresses for the refresh operations.
- The refresh selection signal generator generates selection signals for the normal and hammer refresh operations.
- The selector selects the appropriate row address based on the selection signals.
Potential applications of this technology:
- Memory systems in electronic devices such as computers, smartphones, and tablets.
- Data storage in cloud computing and data centers.
- Embedded systems in automotive, aerospace, and industrial applications.
Problems solved by this technology:
- Ensures the reliability and stability of memory cells by performing regular refresh operations.
- Prevents data corruption and loss due to charge leakage in memory cells.
- Reduces the occurrence of bit flips and soft errors in memory cells.
Benefits of this technology:
- Improved memory cell reliability and data integrity.
- Enhanced performance and longevity of memory systems.
- Reduced risk of data loss and system crashes.
- Increased efficiency and productivity in computing and data storage.
Original Abstract Submitted
A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a memory cell array, a normal refresh row address generator, a hammer refresh row address generator, a refresh selection signal generator, and a selector. The normal and hammer refresh row address generators generates a normal refresh row address and a hammer refresh row address, respectively, in response to a refresh counting control signal. The refresh selection signal generator sequentially generates normal and hammer refresh selection signals in response to the refresh counting control signal. The selector selects the normal refresh row address or the hammer refresh row address in response to the normal and hammer refresh selection signals. A normal refresh operation and a hammer refresh operation are sequentially performed on a memory cell array block among plural memory cell array blocks in response to the refresh row address.
