18081900. PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
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PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
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PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18081900 titled 'PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Simplified Explanation
The patent application describes a package substrate that includes a core insulation layer with two package regions and a boundary region between them. It also includes upper and lower conductive patterns, as well as insulation patterns that partially expose the conductive patterns.
- The package substrate has a core insulation layer with two package regions and a boundary region.
- There are upper and lower conductive patterns in each package region.
- Insulation patterns are present on the core insulation layer and partially expose the conductive patterns.
- The insulation patterns include trenches at the boundary region and reinforcing portions within the trenches.
Potential applications of this technology:
- Electronic packaging for integrated circuits
- Printed circuit boards
- Semiconductor devices
Problems solved by this technology:
- Provides a structure for package substrates that allows for efficient routing of electrical signals
- Helps to prevent short circuits and other electrical issues
- Improves the overall performance and reliability of electronic devices
Benefits of this technology:
- Simplifies the manufacturing process for package substrates
- Enhances the electrical performance of electronic devices
- Reduces the risk of electrical failures and damage to components
Original Abstract Submitted
A package substrate includes: a core insulation layer having first and second package regions and a boundary region between the first and second package regions; a first upper conductive pattern in the first package region; a second upper conductive pattern in the second package region; a first insulation pattern on the core insulation layer to partially expose the first and second upper conductive patterns, wherein the first insulation pattern includes a first trench at the boundary region, and first reinforcing portions in the first trench; a first lower conductive pattern in the first package region; a second lower conductive pattern in the second package region; and a second insulation pattern on the core insulation layer to partially expose the first and second lower conductive patterns, wherein the second insulation pattern includes a second trench at the boundary region, and second reinforcing portions in the second trench.
