18075226. TRANSMITTER AND SHORTENING METHOD THEREOF simplified abstract (Samsung Electronics Co., Ltd.)
Contents
TRANSMITTER AND SHORTENING METHOD THEREOF
Organization Name
Inventor(s)
Hong-sil Jeong of Suwon-si (KR)
TRANSMITTER AND SHORTENING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18075226 titled 'TRANSMITTER AND SHORTENING METHOD THEREOF
Simplified Explanation
The abstract describes a transmitter that includes an outer encoder, a zero padder, and an LDPC encoder. The outer encoder encodes input bits to generate outer-encoded bits, which include input bits and parity bits. The zero padder then adds zero bits to the outer-encoded bits to form LDPC information bits. The LDPC encoder encodes the LDPC information bits, which are divided into multiple bit groups. The zero padder pads zero bits to some of the bit groups based on a predetermined shortening pattern, which ensures that these groups are not sequentially arranged in the LDPC information bits.
- The transmitter includes an outer encoder that encodes input bits and generates outer-encoded bits.
- A zero padder adds zero bits to the outer-encoded bits to form LDPC information bits.
- An LDPC encoder then encodes the LDPC information bits.
- The LDPC information bits are divided into multiple bit groups.
- The zero padder pads zero bits to some of the bit groups based on a predetermined shortening pattern.
- The shortening pattern ensures that the padded bit groups are not sequentially arranged in the LDPC information bits.
Potential Applications
- Communication systems
- Wireless networks
- Data transmission technologies
Problems Solved
- Efficient encoding of input bits
- Improving the performance of LDPC encoding
- Enhancing the reliability of data transmission
Benefits
- Increased data transmission efficiency
- Improved error correction capabilities
- Enhanced reliability and accuracy of transmitted data
Original Abstract Submitted
A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.
