18061827. MEMORY DEVICE simplified abstract (Kioxia Corporation)
Contents
MEMORY DEVICE
Organization Name
Inventor(s)
Masaharu Wada of Yokohama Kanagawa (JP)
MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18061827 titled 'MEMORY DEVICE
Simplified Explanation
The abstract describes a patent application for a circuit configuration involving multiple transistors and inverters. Here is a simplified explanation of the abstract:
- The circuit includes two inverters, each consisting of two transistors.
- The third and fourth nodes are connected to the second and third transistors of the first and second inverters, respectively.
- A sixth transistor is placed between the gate of the fifth transistor and the third node.
- A seventh transistor is placed between the gate of the third transistor and the fourth node.
- An eighth transistor is placed between the gate of the third transistor and the third node.
- A ninth transistor is placed between the gate of the fifth transistor and the fourth node.
- The gates of the eighth and ninth transistors experience a decrease in voltage at a specific time.
- A state is formed with specific voltages applied to the first and second nodes of the first and second inverters at a different time.
- The voltage of the sixth and seventh transistors' gates increases between the first and second times.
Potential applications of this technology:
- Integrated circuits and semiconductor devices
- Digital logic circuits
- Power management systems
- Signal processing circuits
Problems solved by this technology:
- Efficient control of voltage levels in a circuit
- Improved performance and reliability of inverters
- Reduction of power consumption
- Enhanced signal processing capabilities
Benefits of this technology:
- Higher efficiency and reliability in circuit operation
- Lower power consumption and energy savings
- Improved signal processing accuracy and speed
- Increased flexibility in circuit design and integration
Original Abstract Submitted
A first inverter includes second and third transistors coupled at a third node. A second inverter includes fourth and fifth transistors coupled at a fourth node. A sixth transistor is between the fifth transistor's gate and the third node. A seventh transistor is between the third transistor's gate and the fourth node. An eighth transistor is between the third transistor's gate and the third node. A ninth transistor is between the fifth transistor's gate and the fourth node. A voltage of the eighth and ninth transistors' gates lowers at a first time. A state is formed with voltages applied to first and second nodes of the first and second inverters at a second time. A voltage of the sixth and seventh transistors' gates rises between the first and second times.
