18059522. Receiver Circuits simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
Receiver Circuits
Organization Name
Inventor(s)
Taejin Kim of Hwaseong-si (KR)
Receiver Circuits - A simplified explanation of the abstract
This abstract first appeared for US patent application 18059522 titled 'Receiver Circuits
Simplified Explanation
The patent application describes a receiver circuit that includes data lane modules, a clock lane module, a bias current controller, and a link layer. The circuit is designed to operate in different power modes and control the clock bias current based on the power mode.
- The receiver circuit consists of data lane modules, a clock lane module, a bias current controller, and a link layer.
- Each data lane module receives data signals, while the clock lane module receives clock signals and provides divided clock signals to the data lane modules.
- The bias current controller controls the clock bias current, which is the current used to bias the clock lane module.
- The link layer provides a bias control signal to the bias current controller and clock gating signals to the clock lane module based on low power data and clock signals.
- The bias current controller adjusts the clock bias current based on the bias control signal, providing different magnitudes of current in different power modes.
Potential applications of this technology:
- High-speed data communication systems
- Integrated circuits and semiconductor devices
- Networking equipment and devices
Problems solved by this technology:
- Power consumption optimization in receiver circuits
- Efficient use of clock bias current in different power modes
Benefits of this technology:
- Improved power efficiency in receiver circuits
- Enhanced performance and reliability of data communication systems
- Flexibility in adjusting clock bias current based on power requirements
Original Abstract Submitted
A receiver circuit includes data lane modules, a clock lane module, a bias current controller and a link layer. Each of the data lane modules receive respective data signals. The clock lane module receives clock signals and provides each of the data lane modules with a respective divided clock signal among divided clock signals. The bias current controller controls a clock bias current. The link layer provides a bias control signal to the bias current controller and provides clock gating signals to the clock lane module, based on low power data signals low power clock signals. The bias current controller, based on the bias control signal, provides the clock bias current having a first magnitude to the clock lane module in a second power mode and provides the clock bias current having a second magnitude to the clock lane module in a third power mode.
