18059462. BUILT-IN SELF-TEST CIRCUITS FOR MEMORY SYSTEMS HAVING MULTIPLE CHANNELS simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

BUILT-IN SELF-TEST CIRCUITS FOR MEMORY SYSTEMS HAVING MULTIPLE CHANNELS

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Jaewon Park of Suwon-si (KR)

Shinhaeng Kang of Suwon-si (KR)

BUILT-IN SELF-TEST CIRCUITS FOR MEMORY SYSTEMS HAVING MULTIPLE CHANNELS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18059462 titled 'BUILT-IN SELF-TEST CIRCUITS FOR MEMORY SYSTEMS HAVING MULTIPLE CHANNELS

Simplified Explanation

The patent application describes a memory system that includes multiple memory devices, a shared bus, and a memory controller with a built-in self-test (BIST) circuit. The BIST circuit is connected to the memory devices and is used to transfer test patterns and trigger signals to the memory devices via the bus.

• The memory system includes multiple memory devices with arrays of memory cells.
• The memory devices are connected to a shared bus.
• The memory controller has a built-in self-test (BIST) circuit.
• The BIST circuit is connected to the memory devices.
• The BIST circuit transfers a command set with a test pattern to the memory devices via the bus.
• The BIST circuit also transfers a command trigger signal to drive the test pattern to the memory devices via the bus.

Potential applications of this technology:

• Memory testing and verification in various electronic devices such as computers, smartphones, and embedded systems.
• Quality control and manufacturing testing of memory devices.
• Debugging and troubleshooting memory-related issues in electronic systems.

Problems solved by this technology:

• Efficient and centralized memory testing and verification.
• Simplified testing process by using a shared bus and a built-in self-test circuit.
• Cost-effective memory testing solution by eliminating the need for external testing equipment.

Benefits of this technology:

• Improved reliability and performance of memory devices through comprehensive testing.
• Reduced testing time and effort by utilizing the built-in self-test circuit.
• Cost savings by eliminating the need for additional testing equipment.
• Enhanced product quality and customer satisfaction through reliable memory testing.

Original Abstract Submitted

A memory system includes a plurality of memory devices having respective arrays of memory cells therein, a bus electrically coupled to and shared by the plurality of memory devices, and a memory controller. The memory controller, which is electrically coupled to the bus, includes a built-in self-test (BIST) circuit, which is commonly connected to the plurality of memory devices. The BIST circuit is configured to transfer a command set including a test pattern to the plurality of memory devices via the bus, and transfer a command trigger signal for driving the test pattern to the plurality of memory devices via the bus.