18052412. MEMORY CELL ARRAY INCLUDING PARTITIONED DUAL LINE STRUCTURE AND DESIGN METHOD THEREOF simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
MEMORY CELL ARRAY INCLUDING PARTITIONED DUAL LINE STRUCTURE AND DESIGN METHOD THEREOF
Organization Name
Inventor(s)
Sangyeop Baeck of Suwon-si (KR)
MEMORY CELL ARRAY INCLUDING PARTITIONED DUAL LINE STRUCTURE AND DESIGN METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18052412 titled 'MEMORY CELL ARRAY INCLUDING PARTITIONED DUAL LINE STRUCTURE AND DESIGN METHOD THEREOF
Simplified Explanation
The abstract describes an integrated circuit that includes multiple bit lines arranged in a first direction and extending in a second direction. Each bit line consists of a first metal wiring, a third metal wiring, and two bridges connecting them.
- The integrated circuit includes multiple bit lines arranged in a first direction and extending in a second direction.
- Each bit line is composed of a first metal wiring, a third metal wiring, and two bridges connecting them.
- The first metal wiring has a first portion and a second portion separated by a cutting portion.
- The third metal wiring partially overlaps the first metal wiring in a direction perpendicular to the first and second directions.
- The two bridges electrically connect the first metal wiring to the third metal wiring.
Potential applications of this technology:
- Integrated circuits in electronic devices such as smartphones, computers, and IoT devices.
- Memory modules and storage devices.
- Microprocessors and other complex electronic systems.
Problems solved by this technology:
- Efficiently connecting multiple bit lines in an integrated circuit.
- Minimizing interference and signal loss between bit lines.
- Improving the overall performance and reliability of the integrated circuit.
Benefits of this technology:
- Enhanced data transfer and processing capabilities.
- Improved signal integrity and reduced noise.
- Higher efficiency and reliability of integrated circuits.
- Potential for smaller and more compact electronic devices.
Original Abstract Submitted
An integrated circuit includes is provided. The integrated circuit includes: a plurality of bit lines spaced apart from each other along a first direction and extending in a second direction perpendicular to the first direction through a first sub-array and a second sub-array neighboring the first sub-array in the second direction. Each of the plurality of bit lines includes: a first metal wiring extending in the second direction, the first metal wiring including a first portion and a second portion that is separated from the first portion by a first cutting portion; a third metal wiring extending in the second direction, and at least partially overlapping the first metal wiring along a third direction perpendicular to the first direction and the second direction; and two bridges electrically connecting the first metal wiring to the third metal wiring.
