18049001. VOLATILE MEMORY DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
VOLATILE MEMORY DEVICE
Organization Name
Inventor(s)
Kwang Sook Noh of Suwon-si (KR)
VOLATILE MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18049001 titled 'VOLATILE MEMORY DEVICE
Simplified Explanation
The abstract describes a memory device that has a reduced area and is capable of storing and retrieving data.
- The memory device includes two sense amplifiers that are spaced apart from each other.
- A normal mat is placed between the two sense amplifiers and includes two bit lines, each connected to one of the sense amplifiers.
- A reference mat is placed on top of the normal mat and also includes two complementary bit lines, each connected to one of the sense amplifiers.
Potential applications of this technology:
- This memory device can be used in various electronic devices such as computers, smartphones, and tablets.
- It can be used in data storage systems, allowing for faster and more efficient data access.
Problems solved by this technology:
- The memory device has a reduced area, making it more compact and suitable for smaller electronic devices.
- The use of two sense amplifiers and two bit lines allows for improved data storage and retrieval capabilities.
Benefits of this technology:
- The reduced area of the memory device allows for more efficient use of space in electronic devices.
- The use of two sense amplifiers and two bit lines improves the performance and reliability of the memory device.
Original Abstract Submitted
A memory such as a volatile memory device capable of having a reduced area is provided. The volatile memory device comprises a first sense amplifier, a second sense amplifier spaced apart from the first sense amplifier, a first normal mat disposed between the first sense amplifier and the second sense amplifier, and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier, and a first reference mat disposed on the first normal mat between the first sense amplifier and the second sense amplifier, and including a first complementary bit line connected to the first sense amplifier and a second complementary bit line connected to the second sense amplifier.
