17992143. APPARATUS AND METHOD WITH IN-MEMORY PROCESSING simplified abstract (Samsung Electronics Co., Ltd.)
Contents
APPARATUS AND METHOD WITH IN-MEMORY PROCESSING
Organization Name
Inventor(s)
Sangjoon Kim of Hwaseong-si (KR)
APPARATUS AND METHOD WITH IN-MEMORY PROCESSING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17992143 titled 'APPARATUS AND METHOD WITH IN-MEMORY PROCESSING
Simplified Explanation
The patent application describes an apparatus for performing in-memory processing using a memory cell array and a sampling circuit. The apparatus is designed to perform time-digital conversion by comparing a reference voltage and a currently charged voltage in a capacitor.
- The apparatus includes a memory cell array with memory cells that can output a current sum of a column current flowing in respective column lines based on an input signal applied to row lines.
- A sampling circuit is connected to each of the column lines and includes a capacitor that can be charged by a sampling voltage corresponding to the current sum of the column lines.
- A processing circuit is configured to compare a reference voltage and the currently charged voltage in the capacitor when a trigger pulse is generated at a timing corresponding to a quantization level.
- The quantization levels are time-sectioned based on the charge time of the capacitor, and the processing circuit determines the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.
Potential applications of this technology:
- In-memory processing: The apparatus can be used for performing computations directly within the memory cell array, reducing the need for data transfer between memory and processing units.
- Signal processing: The time-digital conversion capability of the apparatus can be utilized for various signal processing applications, such as audio and video processing.
- Machine learning: The in-memory processing and time-digital conversion capabilities can be beneficial for accelerating machine learning algorithms that require large-scale data processing.
Problems solved by this technology:
- Data transfer bottleneck: By performing computations directly within the memory cell array, the apparatus reduces the need for frequent data transfer between memory and processing units, overcoming the bottleneck associated with data transfer.
- Power efficiency: In-memory processing can significantly reduce power consumption compared to traditional computing architectures, as it eliminates the need for data movement and reduces the number of memory accesses.
- Time-digital conversion accuracy: The apparatus provides an accurate and efficient method for converting analog signals to digital signals by utilizing the charge time of the capacitor and comparing it to a reference voltage.
Benefits of this technology:
- Improved performance: By performing computations directly within the memory cell array, the apparatus can achieve faster processing speeds and lower latency compared to traditional computing architectures.
- Power savings: In-memory processing reduces power consumption by minimizing data movement and memory accesses, leading to improved energy efficiency.
- Compact design: The integration of in-memory processing and time-digital conversion in a single apparatus allows for a more compact and streamlined system design.
Original Abstract Submitted
An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.
