17988140. ERROR CORRECTION CODE CIRCUIT, MEMORY DEVICE INCLUDING ERROR CORRECTION CODE CIRCUIT, AND OPERATION METHOD OF ERROR CORRECTION CODE CIRCUIT simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
ERROR CORRECTION CODE CIRCUIT, MEMORY DEVICE INCLUDING ERROR CORRECTION CODE CIRCUIT, AND OPERATION METHOD OF ERROR CORRECTION CODE CIRCUIT
Organization Name
Inventor(s)
Sung-Rae Kim of Hwaseong-si (KR)
Sunghye Cho of Hwaseong-si (KR)
Jin-Hoon Jang of Uiwang-si (KR)
ERROR CORRECTION CODE CIRCUIT, MEMORY DEVICE INCLUDING ERROR CORRECTION CODE CIRCUIT, AND OPERATION METHOD OF ERROR CORRECTION CODE CIRCUIT - A simplified explanation of the abstract
This abstract first appeared for US patent application 17988140 titled 'ERROR CORRECTION CODE CIRCUIT, MEMORY DEVICE INCLUDING ERROR CORRECTION CODE CIRCUIT, AND OPERATION METHOD OF ERROR CORRECTION CODE CIRCUIT
Simplified Explanation
The patent application describes a memory device with an error correction code (ECC) circuit that improves the decoding process and provides error-corrected data and a decoding status flag to a memory controller.
- The memory device includes a memory cell array that stores data and parity data.
- An ECC circuit performs ECC decoding based on the data and parity data.
- The ECC circuit includes a syndrome generator that generates a syndrome based on the data and parity data.
- A syndrome decoding circuit decodes the syndrome to generate an error vector.
- A correction logic circuit generates error-corrected data based on the error vector and the data.
- A fast decoding status flag (DSF) generator generates the decoding status flag based on the syndrome, without the error vector.
Potential applications of this technology:
- Memory devices in various electronic devices such as computers, smartphones, and servers.
- Data storage systems that require reliable and accurate data retrieval.
Problems solved by this technology:
- Errors in data storage can occur due to various factors such as noise, interference, or physical damage.
- ECC decoding helps to identify and correct these errors, ensuring the accuracy and integrity of stored data.
Benefits of this technology:
- Improved ECC decoding process enhances the reliability and accuracy of data retrieval.
- The fast decoding status flag generator provides efficient and timely information about the decoding status.
- Enhanced error correction capabilities lead to improved data integrity and reduced risk of data loss.
Original Abstract Submitted
Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.
