17986021. MEMORY SYSTEMS INCLUDING MEMORY CONTROLLERS THAT USE STATUS INPUT PINS TO CHECK MEMORY OPERATION STATUSES OF MEMORY DEVICES simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
MEMORY SYSTEMS INCLUDING MEMORY CONTROLLERS THAT USE STATUS INPUT PINS TO CHECK MEMORY OPERATION STATUSES OF MEMORY DEVICES
Organization Name
Inventor(s)
Yukyeong Kim of Hwaseong-si (KR)
Donggeun Lim of Yongin-si (KR)
Seonghoon Woo of Hwaseong-si (KR)
MEMORY SYSTEMS INCLUDING MEMORY CONTROLLERS THAT USE STATUS INPUT PINS TO CHECK MEMORY OPERATION STATUSES OF MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17986021 titled 'MEMORY SYSTEMS INCLUDING MEMORY CONTROLLERS THAT USE STATUS INPUT PINS TO CHECK MEMORY OPERATION STATUSES OF MEMORY DEVICES
Simplified Explanation
The patent application describes a memory system that consists of multiple memory devices and a memory controller. The memory controller has a chip enable (CE) pin that can selectively enable any of the memory devices and a status input pin to receive a signal indicating the memory operation status of the enabled memory device.
- The memory system includes multiple memory devices and a memory controller.
- The memory controller has a chip enable (CE) pin that can enable one of the memory devices.
- The memory controller also has a status input pin to receive a signal indicating the memory operation status of the enabled memory device.
- The signal received at the status input pin has three possible levels: first level for indicating a first status of the memory operation, second level for indicating a second status, and third level for indicating a disabled status of the memory devices.
Potential applications of this technology:
- Computer systems and servers that require efficient memory management.
- Mobile devices and tablets that need to optimize memory usage.
- Embedded systems and IoT devices that rely on memory for data storage and processing.
Problems solved by this technology:
- Efficient memory management by selectively enabling and checking the operation status of memory devices.
- Improved reliability by monitoring the status of memory operations.
- Simplified memory control by using a single memory controller for multiple memory devices.
Benefits of this technology:
- Enhanced performance by enabling only the necessary memory devices.
- Improved system stability by monitoring the memory operation status.
- Cost-effective memory management by utilizing a single memory controller for multiple memory devices.
Original Abstract Submitted
A memory system may include a plurality of first memory devices; and a memory controller that may include a first chip enable (CE) pin configured to output a first CE signal that enables selectively any one of the first memory devices and a first status input pin configured to receive a first output signal indicating a memory operation status of an enabled first memory device from among the first memory devices in a first memory operation status checking period. In the first memory operation status checking period, the first output signal has one of a first level to indicate a first status of the memory operation status of the enabled first memory device, a second level to indicate a second status of the memory operation status of the enabled first memory device, or a third level to indicate a disabled status of the first memory devices.
