17985193. DIGITAL LOOP FILTER OF LOW LATENCY AND LOW OPERATION AND CLOCK DATA RECOVERY CIRCUIT INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
DIGITAL LOOP FILTER OF LOW LATENCY AND LOW OPERATION AND CLOCK DATA RECOVERY CIRCUIT INCLUDING THE SAME
Organization Name
Inventor(s)
DIGITAL LOOP FILTER OF LOW LATENCY AND LOW OPERATION AND CLOCK DATA RECOVERY CIRCUIT INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17985193 titled 'DIGITAL LOOP FILTER OF LOW LATENCY AND LOW OPERATION AND CLOCK DATA RECOVERY CIRCUIT INCLUDING THE SAME
Simplified Explanation
The clock data recovery circuit described in this patent application includes several components that work together to generate a clock signal with the correct phase. Here is a simplified explanation of the abstract:
- The circuit has a bang bang phase detector that compares the phase of the clock signal with the phase of the data to determine if the clock leads or lags the data.
- A digital loop filter receives the output of the phase detector and filters out any input jitter, ensuring a stable signal.
- An accumulator then accumulates the filtered output from the digital loop filter.
- An encoder takes the output of the accumulator and generates a phase interpolation code.
- Finally, a phase interpolator uses the phase interpolation code to generate the clock signal with the desired output phase.
Potential applications of this technology:
- Clock data recovery circuits are commonly used in communication systems, such as high-speed data transmission and networking equipment.
- This technology can also be applied in data storage systems, such as hard drives and solid-state drives, to recover clock signals from the stored data.
Problems solved by this technology:
- Clock data recovery circuits are essential in systems where data is transmitted or stored with a clock signal. This technology solves the problem of accurately recovering the clock signal from the data, even in the presence of noise and jitter.
Benefits of this technology:
- The bang bang phase detector and digital loop filter combination provide a robust and efficient method for accurately determining the phase relationship between the clock signal and the data.
- The use of a phase interpolator allows for precise control of the output phase of the clock signal, ensuring synchronization with the data.
- The overall circuit design provides a reliable and efficient clock data recovery solution for various communication and data storage applications.
Original Abstract Submitted
A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.
