17984890. NON-VOLATILE MEMORY DEVICE AND ERASE METHOD THEREOF simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
NON-VOLATILE MEMORY DEVICE AND ERASE METHOD THEREOF
Organization Name
Inventor(s)
NON-VOLATILE MEMORY DEVICE AND ERASE METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 17984890 titled 'NON-VOLATILE MEMORY DEVICE AND ERASE METHOD THEREOF
Simplified Explanation
The abstract describes a non-volatile memory device that consists of multiple cell strings arranged vertically. Each cell string contains multiple memory cells connected to word lines. The device also includes an erase control transistor that connects to the memory cells and cell strings. A row decoder is used to apply different bias voltages to the word lines during different periods.
- The device is a non-volatile memory device with multiple cell strings and memory cells.
- Each cell string is connected to multiple word lines.
- An erase control transistor is used to connect the memory cells and cell strings.
- A row decoder is responsible for applying bias voltages to the word lines.
- During the first period, a first bias voltage is applied to the word lines as the erase voltage increases.
- In the second period, a second bias voltage, higher than the first bias voltage, is applied to some of the word lines.
Potential Applications
- Non-volatile memory devices for various electronic devices such as computers, smartphones, and tablets.
- Storage devices for data centers and cloud computing systems.
Problems Solved
- Efficient erasing of memory cells in a non-volatile memory device.
- Improved control of bias voltages during different periods.
Benefits
- Faster and more efficient erasing of memory cells.
- Enhanced reliability and performance of non-volatile memory devices.
- Improved control over bias voltages for better memory cell operation.
Original Abstract Submitted
A non-volatile memory device includes a plurality of cell strings in a vertical direction, each of the plurality of cell strings including a plurality of memory cells respectively connected to a plurality of word lines, and an erase control transistor having a first end connected to at least one of both ends of plurality of memory cells and a second end connected to at least one of both ends of each of the plurality of cell strings, and a row decoder configured to apply a first bias voltage to the plurality of word lines in a first period in which an erase voltage applied to the second end of the erase control transistor increases to a target level and to apply a second bias voltage higher than the first bias voltage to at least some of the plurality of word lines in a second period after the first period.
