17984042. 3DSFET STANDARD CELL ARCHITECTURE WITH SOURCE-DRAIN JUNCTION ISOLATION simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

3DSFET STANDARD CELL ARCHITECTURE WITH SOURCE-DRAIN JUNCTION ISOLATION

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Ming He of San Jose CA (US)

Mehdi Saremi of Danville CA (US)

Rebecca Park of Mountain View CA (US)

Muhammed Ahosan Ul Karim of San Jose CA (US)

Harsono Simka of Saratoga CA (US)

Sungil Park of Hwaseong-si (KR)

Myungil Kang of Hwaseong-si (KR)

Kyungho Kim of Hwaseong-si (KR)

Doyoung Choi of Hwaseong-si (KR)

JaeHyun Park of Hwaseong-si (KR)

3DSFET STANDARD CELL ARCHITECTURE WITH SOURCE-DRAIN JUNCTION ISOLATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17984042 titled '3DSFET STANDARD CELL ARCHITECTURE WITH SOURCE-DRAIN JUNCTION ISOLATION

Simplified Explanation

The abstract describes a three-dimensionally stacked field-effect transistor (3DSFET) device. Here is a simplified explanation of the abstract:

• The device consists of lower and upper source/drain regions connected through channel structures controlled by a gate structure.
• The lower source/drain regions are connected to each other through a lower channel structure.
• The upper source/drain regions are located above the lower source/drain regions and are connected to each other through an upper channel structure.
• A PN junction is formed between the lower and upper source/drain regions.

Bullet points explaining the patent/innovation:

• Three-dimensionally stacked field-effect transistor (3DSFET) device design.
• Integration of lower and upper source/drain regions through channel structures.
• PN junction formed between the lower and upper source/drain regions.

Potential applications of this technology:

• Integrated circuits and microprocessors.
• High-performance computing.
• Mobile devices and smartphones.
• Power electronics and energy-efficient devices.

Problems solved by this technology:

• Improved transistor performance and efficiency.
• Enhanced integration and miniaturization of electronic devices.
• Reduction of power consumption and heat generation.

Benefits of this technology:

• Higher transistor density and improved performance.
• Increased functionality and capabilities of electronic devices.
• Energy efficiency and reduced power consumption.
• Enhanced integration and miniaturization of electronic components.

Original Abstract Submitted

Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a 1lower source/drain region and a 2lower source/drain region connected to each other through a 1lower channel structure controlled by a 1gate structure; and a 1upper source/drain region and a 2upper source/drain regions, respectively above the 1lower source/drain region and the 2lower source/drain region, and connected to each other through a 1upper channel structure controlled by the 1gate structure, wherein the 2lower source/drain region and the 2upper source/drain region form a PN junction therebetween.