17984025. 3D STACKED FIELD-EFFECT TRANSISTOR DEVICE WITH PN JUNCTION STRUCTURE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

3D STACKED FIELD-EFFECT TRANSISTOR DEVICE WITH PN JUNCTION STRUCTURE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Ming He of San Jose CA (US)

Mehdi Saremi of Danville CA (US)

Rebecca Park of Mountain View CA (US)

Muhammed Ahosan Ul Karim of San Jose CA (US)

Harsono Simka of Saratoga CA (US)

Sungil Park of Hwaseong-si (KR)

Myungil Kang of Hwaseong-si (KR)

Kyungho Kim of Hwaseong-si (KR)

Doyoung Choi of Hwaseong-si (KR)

JaeHyun Park of Hwaseong-si (KR)

3D STACKED FIELD-EFFECT TRANSISTOR DEVICE WITH PN JUNCTION STRUCTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17984025 titled '3D STACKED FIELD-EFFECT TRANSISTOR DEVICE WITH PN JUNCTION STRUCTURE

Simplified Explanation

The abstract describes a three-dimensionally stacked field-effect transistor (3DSFET) device. Here is a simplified explanation of the abstract:

• The device consists of a lower source/drain region of a certain polarity type connected to a lower channel structure.
• There is an upper source/drain region of a different polarity type connected to an upper channel structure, located above the lower source/drain region.
• A PN junction structure is present between the lower and upper source/drain regions, which isolates them electrically.
• The PN junction structure includes a region of the same polarity type as the lower source/drain region and a region of the opposite polarity type as the upper source/drain region.

Potential applications of this technology:

• Integrated circuits: The 3DSFET device can be used in the fabrication of integrated circuits, enabling higher performance and compact designs.
• Semiconductor devices: This technology can be applied to various semiconductor devices, such as transistors, amplifiers, and memory cells, improving their functionality and efficiency.

Problems solved by this technology:

• Electrical isolation: The PN junction structure effectively isolates the upper and lower source/drain regions, preventing unwanted electrical interactions.
• Performance enhancement: The three-dimensional stacking of the transistor components allows for improved performance, such as faster switching speeds and reduced power consumption.

Benefits of this technology:

• Compact design: The three-dimensional stacking enables a higher density of transistors in a smaller area, leading to more compact and efficient electronic devices.
• Improved performance: The 3DSFET device offers enhanced performance characteristics, including faster operation and lower power consumption.
• Integration flexibility: This technology can be integrated into existing semiconductor fabrication processes, allowing for easy adoption and compatibility with current manufacturing techniques.

Original Abstract Submitted

Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a lower source/drain region of a 1polarity type connected to a lower channel structure; an upper source/drain region of a 2polarity type, connected to an upper channel structure, above the lower source/drain region; and a PN junction structure, between the lower source/drain region and the upper source/drain region, configured to electrically isolate the upper source/drain region from the lower source/drain region, wherein the PN junction structure includes a 1region of the 1polarity type and a 2region of the 2polarity type.