17979233. SEMICONDUCTOR PACKAGES HAVING UPPER CONDUCTIVE PATTERNS simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR PACKAGES HAVING UPPER CONDUCTIVE PATTERNS

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Kwangok Jeong of Gwangmyeong-si (KR)

SEMICONDUCTOR PACKAGES HAVING UPPER CONDUCTIVE PATTERNS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17979233 titled 'SEMICONDUCTOR PACKAGES HAVING UPPER CONDUCTIVE PATTERNS

Simplified Explanation

The abstract describes a semiconductor package that includes various components such as a lower redistribution structure, a connection substrate, a semiconductor chip, an encapsulant, and an upper redistribution structure.

  • The lower redistribution structure consists of a wiring layer and a via connected to the wiring layer.
  • The connection substrate is placed on the lower redistribution structure and includes a base layer, lower conductive patterns, first upper conductive patterns (including an upper pad), and a second upper conductive pattern.
  • The semiconductor chip is positioned on the lower redistribution structure and within a cavity of the connection substrate.
  • An encapsulant covers the lower redistribution structure, connection substrate, and semiconductor chip.
  • The upper redistribution structure is located on the encapsulant and includes a redistribution via connected to the second upper conductive pattern.

Potential applications of this technology:

  • Semiconductor packaging for various electronic devices such as smartphones, tablets, and computers.
  • Integrated circuits and microprocessors used in consumer electronics, automotive systems, and industrial equipment.

Problems solved by this technology:

  • Provides a compact and efficient way to package semiconductor chips.
  • Enhances the electrical connectivity and reliability of the package.

Benefits of this technology:

  • Improved performance and functionality of electronic devices.
  • Reduced size and weight of semiconductor packages.
  • Enhanced durability and reliability of the package.


Original Abstract Submitted

A semiconductor package includes a lower redistribution structure including a wiring layer, and a via connected to the wiring layer, a connection substrate on the lower redistribution structure, the connection substrate including a base layer, lower conductive patterns in the base layer, first upper conductive patterns disposed on the base layer, the first upper conductive patterns including an upper pad, and a second upper conductive pattern disposed on the upper pad, a semiconductor chip disposed on the lower redistribution structure and disposed in a cavity of the connection substrate, an encapsulant covering the lower redistribution structure, the connection substrate and the semiconductor chip, and an upper redistribution structure on the encapsulant. The upper redistribution structure includes a redistribution via connected to the second upper conductive pattern.

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