17970777. SEMICONDUCTOR DEVICE HAVING STEPPED MULTI-STACK TRANSISTOR STRUCTURE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR DEVICE HAVING STEPPED MULTI-STACK TRANSISTOR STRUCTURE
Organization Name
Inventor(s)
Byounghak Hong of Albany NY (US)
Seunghyun Song of Albany NY (US)
Kang III Seo of Albany NY (US)
lnchan Hwang of Schenectady NY (US)
SEMICONDUCTOR DEVICE HAVING STEPPED MULTI-STACK TRANSISTOR STRUCTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17970777 titled 'SEMICONDUCTOR DEVICE HAVING STEPPED MULTI-STACK TRANSISTOR STRUCTURE
Simplified Explanation
The patent application describes a semiconductor device that includes two transistors stacked vertically on top of each other.
- The first transistor, called 1transistor, is formed on a substrate and consists of multiple 1nanosheet layers arranged in a channel set. It also has a gate structure surrounding the nanosheet layers and source/drain regions at both ends of the channel set.
- The second transistor, called 2transistor, is formed above the 1transistor and also includes multiple nanosheet layers arranged in a channel set. It has a gate structure surrounding the nanosheet layers and source/drain regions at both ends of the channel set.
- The width of the channel set in the 1transistor is greater than the width of the channel set in the 2transistor.
- The number of nanosheet layers in the 1transistor is smaller than the number of nanosheet layers in the 2transistor.
- The sum of effective channel widths of the nanosheet layers in the 1transistor is equal to the sum of effective channel widths of the nanosheet layers in the 2transistor.
Potential applications of this technology:
- Integrated circuits: The stacked transistors can be used in the fabrication of integrated circuits, allowing for more compact and efficient designs.
- High-performance computing: The improved transistor structure can enhance the performance of processors and other computing devices, enabling faster and more powerful computations.
- Mobile devices: The smaller size and increased efficiency of the stacked transistors can benefit mobile devices by improving battery life and overall performance.
Problems solved by this technology:
- Space limitations: The vertical stacking of transistors allows for more components to be packed into a smaller area, addressing the issue of limited space in semiconductor devices.
- Performance improvement: The optimized design of the transistors can enhance their performance, leading to faster and more efficient operation.
- Power consumption: The improved efficiency of the transistors can help reduce power consumption, extending the battery life of devices.
Benefits of this technology:
- Compact design: The vertical stacking of transistors allows for a more compact layout, enabling the integration of more components in a smaller space.
- Improved performance: The optimized transistor structure can enhance the speed and efficiency of electronic devices, leading to improved overall performance.
- Energy efficiency: The reduced power consumption of the transistors can contribute to energy savings and longer battery life in portable devices.
Original Abstract Submitted
A semiconductor device include: a substrate; a 1transistor formed above the substrate, the 1transistor including a 1channel set of a plurality of 1nanosheet layers, a 1gate structure surrounding the 1nanosheet layers, and 1and 2source/drain regions at both ends of the 1channel set; and a 2transistor formed above the 1transistor in a vertical direction, the 2transistor including a 2channel set of a plurality of 2nanosheet layers, a 2gate structure surrounding the 2nanosheet layers, and 3and 4source/drain regions at both ends of the 2channel set, wherein the 1channel set has a greater width than the 2channel set, wherein a number of the 1nanosheet layers is smaller than a number of the 2nanosheet layers, and wherein a sum of effective channel widths of the 1nanosheet layers is substantially equal to a sum of effective channel width of the 2nanosheet layers.
