17970477. SAMPLING FRACTIONAL-N PHASE-LOCKED LOOP WITH FEEDBACK SPUR COMPENSATION simplified abstract (Intel Corporation)

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SAMPLING FRACTIONAL-N PHASE-LOCKED LOOP WITH FEEDBACK SPUR COMPENSATION

Organization Name

Intel Corporation

Inventor(s)

Hao Luo of Milpitas CA (US)

Somnath Kundu of Hillsboro OR (US)

Brent R. Carlton of Portland OR (US)

SAMPLING FRACTIONAL-N PHASE-LOCKED LOOP WITH FEEDBACK SPUR COMPENSATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17970477 titled 'SAMPLING FRACTIONAL-N PHASE-LOCKED LOOP WITH FEEDBACK SPUR COMPENSATION

Simplified Explanation

The patent application describes a sampling phase-locked loop (PLL) with a compensation circuit to reduce ripples caused by a fractional N divider. The compensation circuit includes a ripple amplifier and a ripple divider to minimize the impact of the ripples on the PLL's performance.

  • The ripple amplifier in the compensation circuit amplifies the AC components of the output voltage from the main sampling circuit of the PLL.
  • The amplified voltage is then processed by a ripple integrator, which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp).
  • The op amp output is fed back to a digital-to-analog converter (DAC) to generate a compensation voltage (Vcomp), which is added to the main output voltage to produce a final control voltage (Vctrl) for the voltage-controlled oscillator (VCO) of the PLL.

Potential Applications

This technology could be applied in various communication systems, radar systems, and frequency synthesizers where precise frequency control is required.

Problems Solved

1. Reduction of ripples in PLLs due to the use of a fractional N divider. 2. Improved stability and accuracy in frequency control systems.

Benefits

1. Enhanced performance and reliability of PLLs. 2. Minimization of frequency inaccuracies and disturbances. 3. Increased precision in frequency synthesis applications.

Potential Commercial Applications

"Enhancing Frequency Control in Communication Systems with Sampling PLL Compensation Circuit"

Possible Prior Art

There may be prior art related to compensation circuits in PLLs to reduce ripples caused by fractional N dividers, but specific examples are not provided in this patent application.

Unanswered Questions

How does the compensation circuit impact the overall power consumption of the PLL system?

The patent application does not delve into the power consumption implications of the compensation circuit. Further research or testing would be needed to determine the effect on power efficiency.

Are there any limitations to the frequency range over which the compensation circuit can effectively reduce ripples?

The patent application does not specify any limitations on the frequency range. It would be important to investigate the frequency response of the compensation circuit to understand its effectiveness across different frequency ranges.


Original Abstract Submitted

Embodiments herein relate to a sampling phase-locked loop (PLL) with a compensation circuit for reducing ripples due to the use of a fractional N divider. The compensation circuit includes a ripple amplifier and a ripple divider. The ripple amplifier receives an output voltage, Vmain, of a main sampling circuit of the PLL and amplifies its alternating current (AC) components. The amplified output voltage is provided to a ripple integrator which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp). An output of the op amp is fed back to a digital-to-analog converter (DAC), which provides a corresponding compensation voltage, Vcomp. Vcomp is added to Vmain to provide a final output control voltage, Vctrl, to control a voltage-controlled oscillator (VCO) of the PLL.