17967768. CHAINED ACCELERATOR OPERATIONS WITH STORAGE FOR INTERMEDIATE RESULTS simplified abstract (Intel Corporation)

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CHAINED ACCELERATOR OPERATIONS WITH STORAGE FOR INTERMEDIATE RESULTS

Organization Name

Intel Corporation

Inventor(s)

Christopher J. Hughes of Santa Clara CA (US)

Saurabh Gayen of Portland OR (US)

Utkarsh Y. Kakaiya of Folsom CA (US)

Alexander F. Heinecke of San Jose CA (US)

CHAINED ACCELERATOR OPERATIONS WITH STORAGE FOR INTERMEDIATE RESULTS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17967768 titled 'CHAINED ACCELERATOR OPERATIONS WITH STORAGE FOR INTERMEDIATE RESULTS

Simplified Explanation

The abstract describes a chip or apparatus with two accelerators that support chained accelerator operations. The first accelerator accesses input data from system memory, processes it, generates intermediate data, and stores it. The second accelerator receives the intermediate data, processes it, and generates additional data.

  • The apparatus includes a first accelerator and a second accelerator.
  • The first accelerator supports chained accelerator operations.
  • The first accelerator accesses input data from system memory, processes it, generates intermediate data, and stores it.
  • The second accelerator also supports chained accelerator operations.
  • The second accelerator receives the intermediate data, processes it, and generates additional data.

Potential Applications

This technology could be applied in:

  • Data processing systems
  • Artificial intelligence applications
  • High-performance computing

Problems Solved

This technology helps in:

  • Accelerating data processing tasks
  • Improving system memory efficiency
  • Enhancing overall system performance

Benefits

The benefits of this technology include:

  • Faster data processing
  • Reduced system memory usage
  • Enhanced computing capabilities

Potential Commercial Applications

A potential commercial application for this technology could be in:

  • Data centers
  • Cloud computing services
  • High-speed computing devices

Possible Prior Art

One possible prior art for this technology could be:

  • Previous systems with chained accelerator operations

What are the specific technical specifications of the first and second accelerators in the chip or apparatus described in the abstract?

The specific technical specifications of the first accelerator include:

  • Support for chained accelerator operations
  • Ability to access input data from system memory
  • Processing capabilities to generate intermediate data
  • Storage functionality for storing intermediate data

The specific technical specifications of the second accelerator include:

  • Support for chained accelerator operations
  • Ability to receive intermediate data from storage
  • Processing capabilities to generate additional data

How does the chained accelerator operation in this chip or apparatus differ from traditional data processing methods?

The chained accelerator operation in this chip or apparatus differs from traditional data processing methods in that:

  • It allows for a more efficient and streamlined data processing flow
  • It reduces the need for data transfer between system memory and accelerators
  • It enables faster processing of data by utilizing multiple accelerators in a chained operation.


Original Abstract Submitted

A chip or other apparatus of an aspect includes a first accelerator and a second accelerator. The first accelerator has support for a chained accelerator operation. The first accelerator is to be controlled as part of the chained accelerator operation to access an input data from a source memory location in system memory, process the input data, generate first intermediate data, and store the first intermediate data to a storage. The second accelerator also has support for the chained accelerator operation. The second accelerator is to be controlled as part of the chained accelerator operation to receive the first intermediate data from the storage, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. Other apparatus, methods, systems, and machine-readable medium are disclosed.

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