17966034. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract (HUAWEI TECHNOLOGIES CO., LTD.)

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SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Organization Name

HUAWEI TECHNOLOGIES CO., LTD.

Inventor(s)

Ran He of Yokohama (JP)

Chihon Ho of Shanghai (CN)

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 17966034 titled 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The patent application describes a semiconductor device that consists of two wafers bonded together with a contact plug. The first wafer has a dielectric layer with a connection pad, while the second wafer also has a dielectric layer with a connection pad. The contact plug, made of a conductive material, is filled in a vertical through hole and serves to electrically connect the two connection pads.

  • The semiconductor device includes two wafers bonded together with a contact plug.
  • The first wafer has a dielectric layer with a connection pad, and the second wafer also has a dielectric layer with a connection pad.
  • The contact plug is made of a conductive material and is filled in a vertical through hole.
  • The through hole is formed through etching and passes through the first wafer and partially through the second wafer to reach the upper surface and/or sidewall of the second connection pad.

Potential Applications

  • Integrated circuits
  • Microprocessors
  • Memory devices
  • Power devices

Problems Solved

  • Provides a reliable and efficient method for electrically connecting two wafers in a semiconductor device.
  • Enables the integration of multiple components in a compact and space-saving manner.
  • Improves the overall performance and functionality of semiconductor devices.

Benefits

  • Enhanced electrical connectivity between wafers.
  • Increased integration density and miniaturization of semiconductor devices.
  • Improved reliability and performance of the device.
  • Cost-effective manufacturing process.


Original Abstract Submitted

The technology of this application relates to a semiconductor device that may include a first wafer, a second wafer, and a contact plug. The first wafer may include a first dielectric layer, and the first dielectric layer has a first connection pad. The second wafer is bonded to the first wafer, the second wafer includes a second dielectric layer, and the second dielectric layer has a second connection pad. The contact plug is made of a conductive material filled in a vertical through hole, and is configured to electrically connect the first connection pad and the second connection pad. The vertical through hole is a through hole that is formed through etching and that passes through the first wafer and partially passes through the second wafer to an upper surface and/or a sidewall of the second connection pad.