17965004. PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
Organization Name
Inventor(s)
Makoto Hirano of Suwon-si (KR)
PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17965004 titled 'PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
Simplified Explanation
The patent application describes a memory device that includes a memory cell array and a page buffer circuit. The page buffer circuit consists of page buffer units, cache units, sensing nodes, and pass transistors.
- The page buffer circuit is made up of upper page buffer units and lower page buffer units, with cache units positioned between them.
- The cache units are divided into upper cache units and lower cache units.
- Each page buffer unit contains a sensing node and a pass transistor.
- The upper cache units share a first combined sensing node, while the lower cache units share a second combined sensing node.
- During data transmission, the sensing nodes in the page buffer units are connected to each other through the pass transistors.
Potential applications of this technology:
- Memory devices in computers, smartphones, and other electronic devices.
- Data storage systems in cloud computing and data centers.
- Solid-state drives (SSDs) and other non-volatile memory devices.
Problems solved by this technology:
- Efficient data transmission and storage in memory devices.
- Improved performance and reliability of memory systems.
- Reduction of power consumption and heat generation.
Benefits of this technology:
- Faster data transfer rates and improved overall system performance.
- Enhanced reliability and durability of memory devices.
- Lower power consumption, leading to longer battery life in portable devices.
Original Abstract Submitted
A memory device includes a memory cell array and a page buffer circuit, wherein the page buffer circuit includes page buffer units including upper page buffer units and lower page buffer units and cache units arranged between the upper page buffer unit and the lower page buffer units. The cache units include upper cache units and lower cache units. Each page buffer unit includes a sensing node and a pass transistor. The upper cache units share a first combined sensing node, and, the lower cache units share a second combined sensing node. In a data transmission period, sensing nodes respectively included the page buffer units are electrically connected to one another through serial connections of the pass transistors respectively included in the page buffer units.
