17961954. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Choong Bin Yim of Seoul (KR)

Ji Hwang Kim of Cheonan-si (KR)

Jin-woo Park of Seoul (KR)

Jong Bo Shim of Asan-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17961954 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Simplified Explanation

The patent application describes a semiconductor package that includes multiple wiring structures and a connecting member.

• The first wiring structure has an insulating layer and a wiring pad inside it.
• The first semiconductor chip is placed on the first wiring structure.
• The second wiring structure is located on top of the first semiconductor chip.
• A connecting member connects the first and second wiring structures.
• The second wiring structure has an insulating layer and multiple wiring pads that directly contact one surface of the first semiconductor chip.

Potential applications of this technology:

• Integrated circuits and electronic devices
• Semiconductor manufacturing industry

Problems solved by this technology:

• Provides a reliable and efficient way to connect multiple wiring structures in a semiconductor package.
• Ensures direct contact between the wiring pads and the semiconductor chip surface.

Benefits of this technology:

• Improved performance and reliability of semiconductor packages.
• Simplified manufacturing process.
• Enhanced electrical connectivity between different components.

Original Abstract Submitted

A semiconductor package includes a first wiring structure which includes a first insulating layer, and a first wiring pad inside the first insulating layer, a first semiconductor chip on the first wiring structure, a second wiring structure on the first semiconductor chip, and a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip.