17960222. STACKED-FET SRAM CELL WITH BOTTOM pFET simplified abstract (International Business Machines Corporation)
Contents
- 1 STACKED-FET SRAM CELL WITH BOTTOM pFET
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 STACKED-FET SRAM CELL WITH BOTTOM pFET - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
STACKED-FET SRAM CELL WITH BOTTOM pFET
Organization Name
International Business Machines Corporation
Inventor(s)
Gen Tsutsui of Glenmont NY (US)
Shogo Mochizuki of Mechanicville NY (US)
Ruilong Xie of Niskayuna NY (US)
STACKED-FET SRAM CELL WITH BOTTOM pFET - A simplified explanation of the abstract
This abstract first appeared for US patent application 17960222 titled 'STACKED-FET SRAM CELL WITH BOTTOM pFET
Simplified Explanation
The semiconductor structure described in the abstract includes a bottom field effect transistor (FET) with bottom source/drain epi regions, a top FET with top source/drain epi regions, a bonding dielectric layer between the two FETs, and a node contact extending from a bottom source/drain epi region of the bottom FET through the bonding dielectric layer and into the top FET. The bottom FET has an inverter gate, while the top FET connects to back-end-of-line components and the bottom FET connects to a backside power delivery network.
- Bottom FET with bottom source/drain epi regions
- Top FET with top source/drain epi regions
- Bonding dielectric layer between the two FETs
- Node contact extending from bottom FET to top FET
- Inverter gate in the bottom FET
- Top FET connects to back-end-of-line components
- Bottom FET connects to backside power delivery network
Potential Applications
This semiconductor structure could be used in:
- Integrated circuits
- Power management systems
- Communication devices
Problems Solved
This technology helps in:
- Improving power delivery efficiency
- Enhancing signal processing capabilities
- Increasing overall performance of electronic devices
Benefits
The benefits of this technology include:
- Higher integration density
- Improved reliability
- Enhanced functionality
Potential Commercial Applications
This technology could be applied in:
- Mobile devices
- Automotive electronics
- Industrial automation systems
Possible Prior Art
One possible prior art for this technology could be:
- Semiconductor structures with similar configurations and functionalities.
Unanswered Questions
How does this technology impact power consumption in electronic devices?
This article does not delve into the specific effects of this technology on power consumption.
What are the manufacturing challenges associated with implementing this semiconductor structure?
The article does not address the potential manufacturing hurdles that may arise when producing this semiconductor structure.
Original Abstract Submitted
A semiconductor structure is presented including a bottom field effect transistor (FET) including a plurality of bottom source/drain (S/D) epi regions, a top FET including a plurality of top S/D epi regions, a bonding dielectric layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from a bottom S/D epi region of the plurality of bottom S/D epi regions of the bottom FET through the bonding dielectric layer and into the top FET. The bottom FET includes an inverter gate. The top FET electrically connects to back-end-of-line (BEOL) components and the bottom FET electrically connects to a backside power delivery network (BSPDN).
