17960050. LATENCY REDUCTION FOR LINK SPEED SWITCHING IN MULTIPLE LANE DATA LINKS simplified abstract (QUALCOMM Incorporated)

From WikiPatents
Jump to navigation Jump to search

LATENCY REDUCTION FOR LINK SPEED SWITCHING IN MULTIPLE LANE DATA LINKS

Organization Name

QUALCOMM Incorporated

Inventor(s)

Prakhar Srivastava of Lucknow (IN)

Santhosh Reddy Akavaram of Hyderabad (IN)

Ravindranath Doddi of Hyderabad (IN)

Ravi Kumar Sepuri of Hyderabad (IN)

LATENCY REDUCTION FOR LINK SPEED SWITCHING IN MULTIPLE LANE DATA LINKS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17960050 titled 'LATENCY REDUCTION FOR LINK SPEED SWITCHING IN MULTIPLE LANE DATA LINKS

Simplified Explanation

The patent application abstract describes an apparatus that can change the data rate of a data link and transfer data traffic between different sets of lanes within the link.

  • The interface circuit provides an interface with a multiple lane data link.
  • The data link has a first set of lanes in an active state and a second set of lanes in an idle state.
  • The controller can receive a request to change the data rate of the data link.
  • The controller changes the second set of lanes from idle to active, trains them to the requested data rate, and transfers data traffic from the first set of lanes to the second set after training.
  • The data traffic is then transmitted on the second set of lanes.

Potential Applications

This technology could be applied in high-speed data transfer systems, such as in networking equipment, storage devices, and communication systems.

Problems Solved

This technology solves the problem of efficiently changing the data rate of a data link and transferring data traffic between different sets of lanes within the link.

Benefits

The benefits of this technology include improved data transfer efficiency, flexibility in adjusting data rates, and optimized use of multiple lanes in a data link.

Potential Commercial Applications

Potential commercial applications of this technology include high-speed networking devices, data storage systems, and communication infrastructure.

Possible Prior Art

One possible prior art for this technology could be existing methods for changing data rates in data links and transferring data traffic between different lanes within a link.

Unanswered Questions

How does this technology compare to existing methods for changing data rates in data links?

This article does not provide a direct comparison to existing methods for changing data rates in data links. It would be helpful to understand the specific advantages or differences of this technology compared to current practices.

What impact could this technology have on overall system performance and data transfer speeds?

The article does not delve into the potential impact of this technology on overall system performance and data transfer speeds. It would be interesting to explore how the efficiency and flexibility provided by this technology could enhance data transfer capabilities in various applications.


Original Abstract Submitted

Aspects relate to link speed for a peripheral component interconnect. In one aspect, an apparatus includes an interface circuit configured to provide an interface with a multiple lane data link, the data link having a first set of lanes in an active state and a second set of lanes in an idle state and a controller. The controller is configured to receive a request at the controller to change a data rate of the data link to a requested data rate, change the second set of lanes from an idle state to an active state, train the second set of lanes to the requested data rate, transfer data traffic from the first set of lanes to the second set of lanes after the training, and transmit the data traffic on the second set of lanes.