17958734. INTRA-BONDING SEMICONDUCTOR INTEGRATED CIRCUIT CHIPS simplified abstract (International Business Machines Corporation)

INTRA-BONDING SEMICONDUCTOR INTEGRATED CIRCUIT CHIPS

Organization Name

International Business Machines Corporation

Inventor(s)

Frank Robert Libsch of White Plains NY (US)

INTRA-BONDING SEMICONDUCTOR INTEGRATED CIRCUIT CHIPS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17958734 titled 'INTRA-BONDING SEMICONDUCTOR INTEGRATED CIRCUIT CHIPS

Simplified Explanation

The patent application describes techniques for bonding multiple semiconductor integrated circuit chips to form multi-chip package structures. Specifically, the invention involves overlapping and bonding two semiconductor dies with arrays of metallic contacts aligned to each other.

• The first semiconductor die has a first overlap region with a first array of metallic contacts.
• The second semiconductor die has a second overlap region with a second array of metallic contacts.
• The first and second overlap regions are overlapped and bonded together with the metallic contacts aligned.
• The semiconductor dies are disposed laterally adjacent to each other.

Potential Applications

This technology could be applied in the manufacturing of advanced electronic devices, such as smartphones, tablets, and computers.

Problems Solved

This innovation addresses the challenge of efficiently connecting multiple semiconductor chips in a compact and reliable manner.

Benefits

The benefits of this technology include improved performance, increased functionality, and enhanced reliability of multi-chip package structures.

Potential Commercial Applications

"Advanced Semiconductor Bonding Techniques for Multi-Chip Packages"

Possible Prior Art

One possible prior art could be the use of wire bonding or flip chip bonding techniques in semiconductor packaging.

Unanswered Questions

How does this technology impact the overall size of the multi-chip package structures?

The article does not provide specific details on how the size of the package structures is affected by this bonding technique.

What materials are used for the metallic contacts in this technology?

The patent application does not mention the specific materials used for the metallic contacts in the semiconductor dies.

Original Abstract Submitted

Techniques are provided for intra-bonding multiple semiconductor integrated circuit chips to form multi-chip package structures. For example, a device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a first overlap region which comprises a first array of metallic contacts. The second semiconductor die comprises a second overlap region which comprises a second array of metallic contacts. The first overlap region and the second overlap region are overlapped and bonded together with the first array of metallic contacts aligned to the second array of metallic contacts, and with the first semiconductor die and the second semiconductor die disposed laterally adjacent to each other.