TECHNOLOGIES FOR ATOMIC LAYER DEPOSITION FOR FERROELECTRIC TRANSISTORS

The patent application describes technologies for a field effect transistor (FET) with a ferroelectric gate dielectric. In one embodiment, a perovskite stack is grown on a buffer layer to manufacture the transistor. The perovskite stack includes doped semiconductor layers alternating with other lattice-matched layers. The doped semiconductor layers are grown on lattice-matched layers to improve their quality. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer is then conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. Finally, a gate is grown on the ferroelectric layer.

Perovskite stack grown on a buffer layer
Doped semiconductor layers grown on lattice-matched layers
Lattice-matched layers etched away to leave fins for a ribbon FET
Ferroelectric layer conformally grown on the fins
Gate grown on the ferroelectric layer

Potential Applications

The technology could be applied in advanced electronic devices, memory storage, and high-speed computing systems.

Problems Solved

The technology solves the problem of improving the quality of doped semiconductor layers in FETs with a ferroelectric gate dielectric.

Benefits

The technology offers enhanced performance, improved efficiency, and increased reliability in electronic devices utilizing FETs with a ferroelectric gate dielectric.

Potential Commercial Applications

The technology could be commercialized in the semiconductor industry for manufacturing high-performance transistors for various electronic applications.

Possible Prior Art

One possible prior art could be the use of ferroelectric materials in memory devices to enhance data retention and switching speed.

Unanswered Questions

How does this technology compare to existing FET designs with traditional gate dielectrics?

The article does not provide a direct comparison between this technology and existing FET designs with traditional gate dielectrics. It would be beneficial to understand the specific advantages and limitations of this technology in comparison to conventional designs.

What are the potential challenges in scaling up this technology for mass production?

The article does not address the potential challenges in scaling up this technology for mass production. It would be important to consider factors such as cost, scalability, and compatibility with existing manufacturing processes.

Original Abstract Submitted

Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.

17958362. TECHNOLOGIES FOR ATOMIC LAYER DEPOSITION FOR FERROELECTRIC TRANSISTORS simplified abstract (Intel Corporation)

Contents

TECHNOLOGIES FOR ATOMIC LAYER DEPOSITION FOR FERROELECTRIC TRANSISTORS

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