17958202. SELF-ALIGNED PATTERNING OF PLATE LINES IN THREE-DIMENSIONAL FERROELECTRIC CAPACITORS simplified abstract (Intel Corporation)

SELF-ALIGNED PATTERNING OF PLATE LINES IN THREE-DIMENSIONAL FERROELECTRIC CAPACITORS

Organization Name

Intel Corporation

Inventor(s)

Christopher M. Neumann of Portland OR (US)

Brian Doyle of Portland OR (US)

Nazila Haratipour of Portland OR (US)

Shriram Shivaraman of Hillsboro OR (US)

Sou-Chi Chang of Portland OR (US)

Uygar E. Avci of Portland OR (US)

Eungnak Han of Portland OR (US)

Manish Chandhok of Beaverton OR (US)

Nafees Aminul Kabir of Hillsboro OR (US)

Gurpreet Singh of Beaverton OR (US)

SELF-ALIGNED PATTERNING OF PLATE LINES IN THREE-DIMENSIONAL FERROELECTRIC CAPACITORS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17958202 titled 'SELF-ALIGNED PATTERNING OF PLATE LINES IN THREE-DIMENSIONAL FERROELECTRIC CAPACITORS

Simplified Explanation

The patent application describes an apparatus with multiple metal layers, metal vias, a ferroelectric material, and a hard mask material for protection and insulation.

• The apparatus includes a first metal layer and a second metal layer stacked on top of each other.
• Metal vias are perpendicular connections between the metal layers, allowing for vertical electrical connections.
• A third metal via extends through both metal layers, providing a pathway for electrical signals.
• A ferroelectric material is sandwiched between the third metal via and the metal layers, enabling memory storage capabilities.
• A hard mask material surrounds portions of the metal vias and the ferroelectric material, protecting them from damage.

Potential Applications

The technology described in this patent application could be used in:

• Memory storage devices
• High-speed data processing systems
• Integrated circuits

Problems Solved

This technology addresses issues related to:

• Vertical integration of metal layers
• Efficient electrical connections between layers
• Protection and insulation of sensitive components

Benefits

The benefits of this technology include:

• Increased memory storage capacity
• Faster data processing speeds
• Enhanced reliability and durability of electronic devices

Potential Commercial Applications

The potential commercial applications of this technology could be in:

• Semiconductor manufacturing
• Consumer electronics
• Telecommunications industry

Possible Prior Art

One possible prior art for this technology could be the use of ferroelectric materials in memory storage devices. Another could be the integration of multiple metal layers in semiconductor devices.

Unanswered Questions

How does the size of the metal vias impact the performance of the apparatus?

The size of the metal vias could affect the electrical conductivity and signal transmission within the apparatus.

What are the limitations of the ferroelectric material in terms of temperature and environmental conditions?

The ferroelectric material may have specific temperature requirements for optimal performance and could be sensitive to certain environmental factors.

Original Abstract Submitted

In one embodiment, an apparatus includes a first metal layer, a second metal layer above the first metal layer, a first metal via generally perpendicular with and connected to the first metal layer, a second metal via generally perpendicular with and connected to the second metal layer, a third metal via generally perpendicular with and extending through the first metal layer and the second metal layer, a ferroelectric material between the third metal via and the first metal layer and between the third metal via and the second metal layer, and a hard mask material around a portion of the first metal via above the first metal layer and the second metal layer, around a portion of the second metal via above the first metal layer and the second metal layer, and around a portion of the ferroelectric material above the first metal layer and the second metal layer.