17957945. DEVICE, METHOD AND SYSTEM TO PROVIDE A RANDOM ACCESS MEMORY WITH A FERROELECTRIC RESISTIVE JUNCTION simplified abstract (Intel Corporation)
Contents
- 1 DEVICE, METHOD AND SYSTEM TO PROVIDE A RANDOM ACCESS MEMORY WITH A FERROELECTRIC RESISTIVE JUNCTION
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 DEVICE, METHOD AND SYSTEM TO PROVIDE A RANDOM ACCESS MEMORY WITH A FERROELECTRIC RESISTIVE JUNCTION - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
DEVICE, METHOD AND SYSTEM TO PROVIDE A RANDOM ACCESS MEMORY WITH A FERROELECTRIC RESISTIVE JUNCTION
Organization Name
Inventor(s)
Sou-Chi Chang of Portland OR (US)
Nazila Haratipour of Portland OR (US)
Saima Siddiqui of HIllsboro OR (US)
Uygar Avci of Portland OR (US)
Chia-Ching Lin of Portland OR (US)
DEVICE, METHOD AND SYSTEM TO PROVIDE A RANDOM ACCESS MEMORY WITH A FERROELECTRIC RESISTIVE JUNCTION - A simplified explanation of the abstract
This abstract first appeared for US patent application 17957945 titled 'DEVICE, METHOD AND SYSTEM TO PROVIDE A RANDOM ACCESS MEMORY WITH A FERROELECTRIC RESISTIVE JUNCTION
Simplified Explanation
The abstract describes a patent application for techniques and mechanisms for storing data using a memory cell with a ferroelectric resistive junction. The memory cell includes a transistor and a ferroelectric resistive junction structure that can provide various levels of resistance to represent different bits.
- The memory cell comprises a transistor and a ferroelectric resistive junction structure.
- The ferroelectric resistive junction structure includes electrode structures and a layer of ferroelectric oxide or semiconductor material.
- The resistance levels of the ferroelectric resistive junction structure represent different bits of data.
- Current flow through the structure is characterized by thermionic emission through a Schottky barrier at an interface with one of the electrode structures.
- The ferroelectric resistive junction structure may also include one or more dielectric layers between the material layer and the electrode structures.
Potential Applications
This technology could be applied in non-volatile memory devices, such as resistive random-access memory (RRAM) or ferroelectric random-access memory (FeRAM).
Problems Solved
This technology solves the problem of achieving high-density, low-power, and fast-access memory storage in electronic devices.
Benefits
The benefits of this technology include faster data storage and retrieval, lower power consumption, and potentially higher memory density compared to traditional memory technologies.
Potential Commercial Applications
Potential commercial applications of this technology include consumer electronics, data storage devices, and embedded systems.
Possible Prior Art
One possible prior art for this technology is the use of ferroelectric materials in memory devices, such as FeRAM, which have been researched and developed for many years.
Unanswered Questions
How does the performance of this memory cell compare to other types of non-volatile memory technologies?
The article does not provide a direct comparison of the performance metrics of this memory cell with other non-volatile memory technologies.
What are the potential challenges or limitations of implementing this technology in practical applications?
The article does not discuss any potential challenges or limitations that may arise when implementing this technology in real-world applications.
Original Abstract Submitted
Techniques and mechanisms for storing data with a memory cell which comprises a ferroelectric (FE) resistive junction. In an embodiment, a memory cell comprises a transistor and a FE resistive junction structure which is coupled to the transistor. The FE resistive junction structure comprises electrode structures, and a layer of a material which is between said electrode structures, wherein the material is a FE oxide or a FE semiconductor. The FE resistive junction structure selectively provides any of various levels of resistance, each to represent a respective one or more bits. A current flow through the FE resistive junction structure is characterized by thermionic emission through a Schottky barrier at an interface with one of the electrode structures. In another embodiment, the FE resistive junction structure further comprises one or more dielectric layers each between the layer of material and a different respective one of the electrode structures.
