17957926. INTEGRATED CIRCUIT PACKAGES WITH HYBRID BONDED DIES AND METHODS OF MANUFACTURING THE SAME simplified abstract (Intel Corporation)

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INTEGRATED CIRCUIT PACKAGES WITH HYBRID BONDED DIES AND METHODS OF MANUFACTURING THE SAME

Organization Name

Intel Corporation

Inventor(s)

Omkar Karhade of Chandler AZ (US)

Nitin Deshpande of Chandler AZ (US)

Harini Kilambi of Portland OR (US)

Jagat Shakya of Hillsboro OR (US)

Debendra Mallik of Chandler AZ (US)

INTEGRATED CIRCUIT PACKAGES WITH HYBRID BONDED DIES AND METHODS OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17957926 titled 'INTEGRATED CIRCUIT PACKAGES WITH HYBRID BONDED DIES AND METHODS OF MANUFACTURING THE SAME

Simplified Explanation

The patent application describes an integrated circuit (IC) package with two dies electrically coupled through metal vias in bonding layers.

  • The IC package includes a first die with a bulk semiconductor region, a second die with a bulk semiconductor region, and bonding layers with metal vias.
  • The first die and second die are electrically coupled through metal vias in the bonding layers.
  • The metal vias in the first bonding layer are in direct contact with the metal vias in the second bonding layer.

Potential Applications

This technology could be applied in:

  • Semiconductor manufacturing
  • Electronic devices

Problems Solved

This technology helps solve issues related to:

  • Electrical coupling between dies
  • Integration of multiple components in a compact space

Benefits

The benefits of this technology include:

  • Improved electrical connectivity
  • Enhanced performance of integrated circuits
  • Compact design for electronic devices

Potential Commercial Applications

A potential commercial application for this technology could be in:

  • Consumer electronics
  • Telecommunications industry

Possible Prior Art

One possible prior art for this technology could be:

  • Existing methods of die bonding and electrical coupling in semiconductor packaging

Unanswered Questions

How does this technology impact the overall size of the integrated circuit package?

This technology allows for a more compact design by enabling efficient electrical coupling between dies.

What are the potential limitations of using metal vias in bonding layers for electrical coupling?

The use of metal vias in bonding layers may have limitations in terms of signal integrity and reliability over time.


Original Abstract Submitted

Methods, apparatus, systems, and articles of manufacture are disclosed includes an integrated circuit (IC) package including a first die including a first surface and a second surface opposite the first surface, the first surface defined by a bulk semiconductor region of the first die, a second die including a third surface and a fourth surface opposite the third surface, the third surface defined by a bulk semiconductor region of the second die, the fourth surface facing towards the second surface, a first bonding layer between the second and fourth surfaces, the first bonding layer including first metal vias disposed therein, and a second bonding layer between the second and fourth surfaces, the second bonding layer including second metal vias disposed therein, the first bonding layer in direct contact with the second bonding layer, ones of the first metal vias in direct contact with ones of the second metal vias to electrically couple the first die to the second die.

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