17957552. BACKSIDE WAFER TREATMENTS TO REDUCE DISTORTIONS AND OVERLAY ERRORS DURING WAFER CHUCKING simplified abstract (Intel Corporation)
Contents
- 1 BACKSIDE WAFER TREATMENTS TO REDUCE DISTORTIONS AND OVERLAY ERRORS DURING WAFER CHUCKING
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 BACKSIDE WAFER TREATMENTS TO REDUCE DISTORTIONS AND OVERLAY ERRORS DURING WAFER CHUCKING - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
BACKSIDE WAFER TREATMENTS TO REDUCE DISTORTIONS AND OVERLAY ERRORS DURING WAFER CHUCKING
Organization Name
Inventor(s)
Tayseer Mahdi of Hillsboro OR (US)
Grant Kloster of Lake Oswego OR (US)
Florian Gstrein of Portland OR (US)
BACKSIDE WAFER TREATMENTS TO REDUCE DISTORTIONS AND OVERLAY ERRORS DURING WAFER CHUCKING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17957552 titled 'BACKSIDE WAFER TREATMENTS TO REDUCE DISTORTIONS AND OVERLAY ERRORS DURING WAFER CHUCKING
Simplified Explanation
The abstract describes methods, device structures, and wafer treatment chemistries related to backside wafer treatments to reduce distortions and overlay errors due to wafer deformation during wafer chucking. A backside layer is applied to the wafer prior to chucking, with chemistry that lowers the surface free energy of the wafer during chucking to eliminate or mitigate wafer deformation during processing.
- Backside layer applied to wafer before chucking
- Chemistry of backside layer reduces surface free energy during chucking
- Aim to eliminate or reduce wafer deformation during processing
Potential Applications
The technology described in the patent application could be applied in the semiconductor industry for wafer processing, particularly in lithography processes where overlay errors due to wafer deformation can impact device performance.
Problems Solved
The technology addresses the issue of wafer deformation during chucking, which can lead to distortions and overlay errors in wafer processing. By applying a backside layer with specific chemistry, the surface free energy of the wafer is lowered, reducing the likelihood of deformation.
Benefits
- Improved accuracy in wafer processing - Reduction in overlay errors - Enhanced device performance due to minimized wafer distortions
Potential Commercial Applications
"Reducing Wafer Deformation in Semiconductor Processing: Applications and Benefits"
Possible Prior Art
There may be prior art related to wafer chucking techniques and backside treatments in the semiconductor industry, but specific examples would need to be researched to determine if they are similar to the technology described in the patent application.
Unanswered Questions
How does the backside layer chemistry specifically lower the surface free energy of the wafer during chucking?
The patent abstract mentions that the chemistry of the backside layer reduces the surface free energy of the wafer during chucking, but it does not provide specific details on the mechanisms behind this process.
What specific types of distortions and overlay errors are commonly encountered in wafer processing due to wafer deformation during chucking?
While the abstract mentions distortions and overlay errors as potential issues resulting from wafer deformation during chucking, it does not specify the types of distortions or errors that are typically observed in semiconductor processing.
Original Abstract Submitted
Methods, device structures, and wafer treatment chemistries related to backside wafer treatments to reduce distortions and overlay errors due to wafer deformation during wafer chucking are described. A backside layer is applied to the wafer prior to chucking. The chemistry of the backside layer lowers the surface free energy of the wafer during chucking to eliminate or mitigate wafer deformation during wafer processing.
