17956775. SPLIT VIA STRUCTURES COUPLED TO CONDUCTIVE LINES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION simplified abstract (Intel Corporation)

SPLIT VIA STRUCTURES COUPLED TO CONDUCTIVE LINES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Organization Name

Intel Corporation

Inventor(s)

Leonard P. Guler of Hillsboro OR (US)

Mohit K. Haran of Hillsboro OR (US)

Nikhil Mehta of Portland OR (US)

Charles H. Wallace of Portland OR (US)

Tahir Ghani of Portland OR (US)

Sukru Yemenicioglu of Portland OR (US)

SPLIT VIA STRUCTURES COUPLED TO CONDUCTIVE LINES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17956775 titled 'SPLIT VIA STRUCTURES COUPLED TO CONDUCTIVE LINES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Simplified Explanation

The patent application describes an integrated circuit structure fabrication method involving multiple conductive lines and vias in different inter-layer dielectric layers.

• The integrated circuit structure includes multiple conductive lines on the same level and direction in a first ILD layer.
• A second ILD layer is above the conductive lines, with straight-edge vias connecting to different conductive lines.
• The vias are laterally spaced apart and have straight edges facing each other.

Potential Applications

This technology can be applied in the fabrication of advanced integrated circuits for various electronic devices, such as smartphones, computers, and IoT devices.

Problems Solved

This technology helps in improving the performance and reliability of integrated circuits by providing efficient interconnection between different conductive lines.

Benefits

The straight-edge vias and spaced-apart conductive lines help in reducing signal interference and improving signal transmission speed within the integrated circuit structure.

Potential Commercial Applications

This technology can be utilized by semiconductor companies and electronics manufacturers to produce high-performance integrated circuits for consumer electronics and industrial applications.

Possible Prior Art

One possible prior art could be the use of traditional via structures in integrated circuit fabrication, which may not offer the same level of signal integrity and performance as the straight-edge vias described in this patent application.

How does this technology compare to existing via structures in terms of signal integrity and performance?

The patent application does not provide a direct comparison with existing via structures, so it is unclear how this technology improves signal integrity and performance.

What are the potential challenges in implementing this technology on a large scale in semiconductor manufacturing processes?

The patent application does not address the potential challenges or limitations of implementing this technology on a large scale, which could include cost, complexity, and compatibility with existing manufacturing processes.

Original Abstract Submitted

Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines in a first inter-layer dielectric (ILD) layer, the plurality of conductive lines on a same level and along a same direction. A second ILD layer is over the plurality of conductive lines and over the first ILD layer. A first conductive via is in a first opening in the second ILD layer, the first conductive via in contact with a first one of the plurality of conductive lines, the first conductive via having a straight edge. A second conductive via is in a second opening in the second ILD layer, the second conductive via in contact with a second one of the plurality of conductive lines, the second one of the plurality of conductive lines laterally spaced apart from the first one of the plurality of conductive lines, and the second conductive via having a straight edge, the straight edge of the second conductive via facing the straight edge of the first conductive via.