17956760. SIDE OF A DIE THAT IS COPLANAR WITH A SIDE OF A MOLDING simplified abstract (Intel Corporation)

SIDE OF A DIE THAT IS COPLANAR WITH A SIDE OF A MOLDING

Organization Name

Intel Corporation

Inventor(s)

Xavier F. Brun of Chandler AZ (US)

Trianggono Widodo of Hillsboro OR (US)

SIDE OF A DIE THAT IS COPLANAR WITH A SIDE OF A MOLDING - A simplified explanation of the abstract

This abstract first appeared for US patent application 17956760 titled 'SIDE OF A DIE THAT IS COPLANAR WITH A SIDE OF A MOLDING

Simplified Explanation

Embodiments herein relate to systems, apparatuses, or processes creating a package that includes a die embedded in a molding, where a surface of the die is coplanar with a surface of the molding. During a stage of package manufacture, the die may have a finished side that may be coupled with a component of the package, and an unfinished side. During a subsequent stage of package manufacture, molding may be placed around the die, and then the molding and at least a portion of the die may be planarized, which may involve grinding and polishing. The planarization may reveal one or more TSV at the side of the die which is now finished and ready for electrical coupling with other components. As a result, a side of the molding at a side of the die to be coplanar. Other embodiments may be described and/or claimed.

• Die embedded in molding with coplanar surfaces
• Die has finished and unfinished sides
• Planarization process involves grinding and polishing
• Reveals TSV for electrical coupling
• Molding side becomes coplanar with die side

Potential Applications

This technology could be applied in semiconductor packaging, microelectronics, and integrated circuit manufacturing.

Problems Solved

This innovation solves the problem of integrating dies into moldings while maintaining coplanar surfaces for electrical coupling.

Benefits

The benefits of this technology include improved electrical coupling efficiency, compact packaging, and enhanced overall performance of electronic devices.

Potential Commercial Applications

Potential commercial applications of this technology include consumer electronics, automotive electronics, and medical devices.

Possible Prior Art

One possible prior art could be the use of flip chip technology in semiconductor packaging to achieve electrical connections between dies and substrates. Another could be the use of wafer-level packaging techniques to embed dies in moldings.

How does the planarization process affect the overall cost of manufacturing these packages?

The cost implications of the planarization process in terms of equipment, materials, and labor need to be further explored to understand its impact on the overall manufacturing cost.

What are the potential challenges in scaling up this technology for mass production?

Scaling up this technology for mass production may pose challenges in terms of consistency, yield rates, and production efficiency, which need to be addressed for successful implementation on a larger scale.

Original Abstract Submitted

Embodiments herein relate to systems, apparatuses, or processes creating a package that includes a die embedded in a molding, where a surface of the die is coplanar with a surface of the molding. During a stage of package manufacture, the die may have a finished side that may be coupled with a component of the package, and an unfinished side. During a subsequent stage of package manufacture, molding may be placed around the die, and then the molding and at least a portion of the die may be planarized, which may involve grinding and polishing. The planarization may reveal one or more TSV at the side of the die which is now finished and ready for electrical coupling with other components. As a result, a side of the molding at a side of the die to be coplanar. Other embodiments may be described and/or claimed.