TECHNOLOGIES FOR PEROVSKITE TRANSISTORS

The patent application describes technologies for a field effect transistor (FET) with a ferroelectric gate dielectric. Here are some key points from the abstract:

Perovskite stack grown on a buffer layer for manufacturing the transistor
Perovskite stack includes doped semiconductor layers alternating with other lattice-matched layers
Doped semiconductor layers can be improved in quality by growing them on lattice-matched layers
Lattice-matched layers can be etched away, leaving doped semiconductor layers as fins for a ribbon FET
Interlayer deposited on top of a semiconductor layer, with a ferroelectric layer on the interlayer to bridge a gap in lattice parameters

Potential Applications

The technology could be applied in the development of high-performance transistors for various electronic devices, such as smartphones, computers, and sensors.

Problems Solved

The technology addresses the need for improved performance and efficiency in semiconductor devices by utilizing a ferroelectric gate dielectric in FETs.

Benefits

The benefits of this technology include enhanced transistor performance, increased efficiency, and potentially lower power consumption in electronic devices.

Potential Commercial Applications

The technology could have commercial applications in the semiconductor industry, particularly in the production of advanced electronic devices with improved performance and energy efficiency.

Possible Prior Art

One possible prior art could be the use of ferroelectric materials in memory devices, but the specific application of a ferroelectric gate dielectric in FETs as described in the patent application may be a novel innovation.

Unanswered Questions

How does the performance of FETs with a ferroelectric gate dielectric compare to traditional FETs in terms of speed and power consumption?

The article does not provide a direct comparison between FETs with a ferroelectric gate dielectric and traditional FETs in terms of speed and power consumption.

Are there any challenges or limitations in implementing this technology on a large scale for commercial production?

The article does not address any potential challenges or limitations in scaling up the production of FETs with a ferroelectric gate dielectric for commercial applications.

Original Abstract Submitted

Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.

17956296. TECHNOLOGIES FOR PEROVSKITE TRANSISTORS simplified abstract (Intel Corporation)

Contents

TECHNOLOGIES FOR PEROVSKITE TRANSISTORS

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