17955978. MEMORY DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
MEMORY DEVICE
Organization Name
Inventor(s)
Kyeong Tae Nam of Suwon-si (KR)
Young Hun Seo of Seongnam-si (KR)
MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17955978 titled 'MEMORY DEVICE
Simplified Explanation
The abstract describes a memory device that includes a memory cell array, a sense amplifier, and various transistors for signal amplification and pre-charging.
- The memory device has a memory cell array connected to a first bit line and a complementary bit line.
- A first bit line sense amplifier is used to sense, amplify, and output signals from the first bit line and the complementary bit line.
- A charge transfer transistor is connected to the first bit line sense amplifier and is controlled by a charge transfer signal.
- An offset transistor connects two nodes based on an offset removal signal.
- A pre-charging transistor is connected between one of the nodes and a pre-charging voltage line, and it pre-charges the first bit line or the complementary bit line based on an equalizing signal.
Potential applications of this technology:
- Memory devices in various electronic devices such as computers, smartphones, and tablets.
- Storage devices in data centers and servers.
Problems solved by this technology:
- Efficient sensing and amplification of signals from memory cells.
- Pre-charging of bit lines to ensure accurate reading and writing of data.
Benefits of this technology:
- Improved performance and reliability of memory devices.
- Enhanced data storage and retrieval capabilities.
- Reduced power consumption and improved energy efficiency.
Original Abstract Submitted
A memory device is provided. The memory device comprises a memory cell array connected to a first bit line and a complementary bit line, a first bit line sense amplifier configured to sense, amplify and the first bit line signal output a first bit line signal and the complimentary bit signal output on a complementary bit line signal output on the first bit line and the complementary bit line, a charge transfer transistor connected to the first bit line sense amplifier and configured to be gated by a charge transfer signal of a first node, an offset transistor configured to connect the first node and a second node based on an offset removal signal and a pre-charging transistor connected between the second node and a pre-charging voltage line and the pre-charging transistor being configured to pre-charge the first bit line or the complementary bit line based on an equalizing signal.
