17954695. METHOD TO AVOID MEMORY BANK CONFLICTS AND PIPELINE CONFLICTS IN TENSOR MEMORY LAYOUT simplified abstract (Huawei Technologies Co., Ltd.)
METHOD TO AVOID MEMORY BANK CONFLICTS AND PIPELINE CONFLICTS IN TENSOR MEMORY LAYOUT
Organization Name
Inventor(s)
Jessica Davies of Markham (CA)
METHOD TO AVOID MEMORY BANK CONFLICTS AND PIPELINE CONFLICTS IN TENSOR MEMORY LAYOUT - A simplified explanation of the abstract
This abstract first appeared for US patent application 17954695 titled 'METHOD TO AVOID MEMORY BANK CONFLICTS AND PIPELINE CONFLICTS IN TENSOR MEMORY LAYOUT
Simplified Explanation
The abstract describes a method for optimizing the layout of a tensor memory, which is used for reading and writing data for a task. The method involves defining hard constraints for allocating input/output (I/O) vectors and applying these constraints to identify potential conflicts between the I/O vectors. Soft constraints are also generated to mitigate these conflicts. The constraints are then applied in a maximum satisfiability (MaxSAT) solver to determine the locations of the data in the tensor memory. The starting addresses of the input and output data for each I/O vector are updated accordingly.
- Method for optimizing the layout of a tensor memory for data reading and writing.
- Defines hard constraints for allocating input/output (I/O) vectors.
- Identifies potential conflicts between the I/O vectors.
- Generates soft constraints to mitigate conflicts.
- Applies constraints in a maximum satisfiability (MaxSAT) solver.
- Determines locations of data in the tensor memory.
- Updates starting addresses of input and output data for each I/O vector.
Potential Applications
- Optimization of tensor memory layout in various computing tasks.
- Efficient allocation of I/O vectors for reading and writing data.
Problems Solved
- Addressing potential conflicts between input/output (I/O) vectors in tensor memory.
- Optimizing the layout of tensor memory for efficient data access.
Benefits
- Improved performance and efficiency in data reading and writing tasks.
- Reduction of conflicts and potential errors in tensor memory layout.
- Enhanced allocation of I/O vectors for optimized data access.
Original Abstract Submitted
A method for optimizing a layout of a tensor memory defines at least one hard constraint for allocating a plurality of input/output (I/O) vectors for reading and writing data for a task in the tensor memory. The at least one hard constraint is applied to determine one or more potential conflicts between the plurality of I/O vectors. One or more soft constraints aimed at mitigating the one or more potential conflicts between the I/O vectors may also be generated. The at least one hard constraint is applied in a maximum satisfiability (MaxSAT) solver. The one or more soft constraints may also be applied in the MaxSAT solver. The MaxSAT solver determines locations of the data in the tensor memory. The starting addresses of the input data to be read and of output data to be written by each of the I/O vectors are updated in the tensor memory.
