17954394. SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
HYEON-WOO Jang of Hwaseong-si (KR)
DONG-WAN Kim of Hwaseong-si (KR)
DONG-SIK Park of Suwon-si (KR)
SOOHO Shin of Hwaseong-si (KP)
JIHOON Chang of Yongin-si (KR)
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17954394 titled 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The patent application describes semiconductor memory devices and their fabrication methods. The memory device includes a semiconductor substrate with a cell array region and a peripheral region. It also includes bottom electrodes, a dielectric layer, and a top electrode. The top electrode is made up of several layers including a first metal layer, a silicon-germanium layer, a second metal layer, and a silicon layer. The amount of boron in the silicon-germanium layer is greater than the amount of boron in the silicon layer.
- The patent application describes a semiconductor memory device with improved performance and reliability.
- The memory device includes a unique top electrode structure with multiple layers.
- The use of a silicon-germanium layer with a higher boron content provides enhanced properties.
- The fabrication method ensures that the dielectric layer conformally covers the bottom electrodes, improving device performance.
Potential Applications
This technology can be applied in various semiconductor memory devices, such as:
- Flash memory
- DRAM (Dynamic Random Access Memory)
- SRAM (Static Random Access Memory)
- Non-volatile memory
Problems Solved
This technology addresses the following problems in semiconductor memory devices:
- Performance limitations due to conventional top electrode structures
- Reliability issues caused by inadequate dielectric layer coverage
- Challenges in achieving high-density memory devices with improved performance
Benefits
The use of this technology offers several benefits:
- Improved performance and reliability of semiconductor memory devices
- Enhanced properties of the top electrode structure with multiple layers
- Better coverage of the dielectric layer, ensuring improved device performance
- Potential for higher-density memory devices with improved performance
Original Abstract Submitted
Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a semiconductor substrate that includes a cell array region and a peripheral region, a plurality of bottom electrodes on the semiconductor substrate on the cell array region, a dielectric layer that conformally covers sidewalls and top surfaces of the bottom electrodes, and a top electrode on the dielectric layer and between the bottom electrodes. The top electrode includes a first metal layer, a silicon-germanium layer, a second metal layer, and a silicon layer that are sequentially stacked. An amount of boron in the silicon-germanium layer is greater than an amount of boron in the silicon layer.
