17953715. MEMORY DEVICE HAVING ROW DECODER ARRAY ARCHITECTURE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

MEMORY DEVICE HAVING ROW DECODER ARRAY ARCHITECTURE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Seungyeon Kim of Suwon-si (KR)

Jooyong Park of Suwon-si (KR)

Hongsoo Jeon of Suwon-si (KR)

MEMORY DEVICE HAVING ROW DECODER ARRAY ARCHITECTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17953715 titled 'MEMORY DEVICE HAVING ROW DECODER ARRAY ARCHITECTURE

Simplified Explanation

The abstract describes a memory device that consists of a peripheral circuit structure and a cell array structure. The cell array structure is divided into a normal cell region and a dummy cell region, with the dummy cell region including a bit line through-electrode region. The peripheral circuit structure includes a row decoder region with a unit row decoder circuit connected to each memory block.

• The memory device includes a peripheral circuit structure and a cell array structure.
• The cell array structure is divided into a normal cell region and a dummy cell region.
• The dummy cell region includes a bit line through-electrode region.
• The peripheral circuit structure includes a row decoder region.
• The row decoder region has a unit row decoder circuit connected to each memory block.
• The bit line through-electrode region is positioned according to the height of the unit row decoder circuit.

Potential applications of this technology:

• Memory devices in electronic devices such as smartphones, tablets, and computers.
• Storage devices in data centers and servers.
• Embedded memory in various electronic systems.

Problems solved by this technology:

• Efficient use of space in memory devices by vertically overlapping the peripheral circuit structure and the cell array structure.
• Improved performance and reliability of memory devices through the use of a bit line through-electrode region in the dummy cell region.

Benefits of this technology:

• Increased memory capacity in a compact form factor.
• Enhanced data access speed and overall performance of memory devices.
• Improved reliability and error correction capabilities in memory operations.

Original Abstract Submitted

A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.