17953068. MEMORY DEVICE THAT STORES NUMBER OF ACTIVATION TIMES OF WORD LINES simplified abstract (Samsung Electronics Co., Ltd.)
Contents
MEMORY DEVICE THAT STORES NUMBER OF ACTIVATION TIMES OF WORD LINES
Organization Name
Inventor(s)
SEONG-JIN Cho of HWASEONG-SI, GYEONGGI-DO (KR)
MEMORY DEVICE THAT STORES NUMBER OF ACTIVATION TIMES OF WORD LINES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17953068 titled 'MEMORY DEVICE THAT STORES NUMBER OF ACTIVATION TIMES OF WORD LINES
Simplified Explanation
The patent application describes a memory device that includes a memory bank array with a first edge memory block, a second edge memory block, and multiple memory blocks in between.
- The memory device has sense amplifiers that connect the bit lines and complementary bit lines of the memory blocks.
- There are also edge sense amplifiers connected to the bit lines and complementary bit lines of the first and second edge memory blocks.
Potential applications of this technology:
- Memory devices used in computers, smartphones, and other electronic devices.
- Storage devices for data centers and cloud computing.
Problems solved by this technology:
- Efficient organization of memory blocks in a memory bank array.
- Improved data access and retrieval speed.
Benefits of this technology:
- Increased memory capacity and performance.
- Enhanced data transfer rates.
- Reduced power consumption.
Original Abstract Submitted
A memory device including a memory bank array which includes a first edge memory block, a second edge memory block, and a plurality of memory blocks placed between the first edge memory block and the second edge memory block; a plurality of sense amplifiers between the plurality of memory blocks, and that connect a first bit line of a memory block on one side of each of the plurality of sense amplifiers and a first complementary bit line of a memory block on an other side of each of the plurality of sense amplifiers; a first edge sense amplifier connected to a second bit line and a second complementary bit line of the first edge memory block; and a second edge sense amplifier connected to a third bit line and a third complementary bit line of the second edge memory block.
