17951712. MEMORY DEVICE FOR INDIVIDUALLY APPLYING VOLTAGES TO WORD LINES ADJACENT TO SELECTED WORD LINE, AND OPERATING METHOD THEREOF simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
MEMORY DEVICE FOR INDIVIDUALLY APPLYING VOLTAGES TO WORD LINES ADJACENT TO SELECTED WORD LINE, AND OPERATING METHOD THEREOF
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MEMORY DEVICE FOR INDIVIDUALLY APPLYING VOLTAGES TO WORD LINES ADJACENT TO SELECTED WORD LINE, AND OPERATING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 17951712 titled 'MEMORY DEVICE FOR INDIVIDUALLY APPLYING VOLTAGES TO WORD LINES ADJACENT TO SELECTED WORD LINE, AND OPERATING METHOD THEREOF
Simplified Explanation
The patent application describes a memory device that includes a memory block and an address decoding circuit. The memory block consists of three word lines arranged perpendicular to a substrate: a first adjacent word line, a selected word line, and a second adjacent word line.
- The address decoding circuit is designed to set up the selected word line during a first setup period.
- During this setup period, the circuit applies a first pre-setup voltage to the first adjacent word line.
- The circuit then applies a higher first setup voltage to the first adjacent word line.
- Simultaneously, a second pre-setup voltage is applied to the second adjacent word line.
- Finally, a higher second setup voltage is applied to the second adjacent word line.
- Importantly, the first pre-setup voltage is higher than the second pre-setup voltage.
Potential applications of this technology:
- Memory devices in electronic devices such as smartphones, tablets, and computers.
- Data storage systems in servers and data centers.
- Embedded memory in various electronic devices.
Problems solved by this technology:
- Efficient and reliable setup of the selected word line in a memory device.
- Minimizing interference between adjacent word lines during the setup process.
- Enhancing the overall performance and stability of the memory device.
Benefits of this technology:
- Improved memory device performance and reliability.
- Reduced power consumption during the setup process.
- Enhanced data storage capabilities in electronic devices.
Original Abstract Submitted
A memory device includes a memory block including a first adjacent word line, a selected word line, and a second adjacent word line provided in a direction perpendicular to a substrate and an address decoding circuit. In a first setup period in which the selected word line is set up, the address decoding circuit is configured to apply a first pre-setup voltage to the first adjacent word line, apply a first setup voltage that is higher than the first pre-setup voltage to the first adjacent word line, apply a second pre-setup voltage to the second adjacent word line, and apply a second setup voltage that is higher than the second pre-setup voltage to the second adjacent word line. The first pre-setup voltage is higher than the second pre-setup voltage.
