17951580. MASK LAYOUT DESIGN METHOD, MASK AND INTEGRATED CIRCUIT MANUFACTURING METHODS, MASKS AND INTEGRATED CIRCUITS simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
- 1 MASK LAYOUT DESIGN METHOD, MASK AND INTEGRATED CIRCUIT MANUFACTURING METHODS, MASKS AND INTEGRATED CIRCUITS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MASK LAYOUT DESIGN METHOD, MASK AND INTEGRATED CIRCUIT MANUFACTURING METHODS, MASKS AND INTEGRATED CIRCUITS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Original Abstract Submitted
MASK LAYOUT DESIGN METHOD, MASK AND INTEGRATED CIRCUIT MANUFACTURING METHODS, MASKS AND INTEGRATED CIRCUITS
Organization Name
Inventor(s)
Somin Cheon of Hwaseong-si (KR)
Joonsung Kim of Hwaseong-si (KR)
Jaewan Song of Hwaseong-si (KR)
MASK LAYOUT DESIGN METHOD, MASK AND INTEGRATED CIRCUIT MANUFACTURING METHODS, MASKS AND INTEGRATED CIRCUITS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17951580 titled 'MASK LAYOUT DESIGN METHOD, MASK AND INTEGRATED CIRCUIT MANUFACTURING METHODS, MASKS AND INTEGRATED CIRCUITS
Simplified Explanation
The patent application describes a method for designing a crack-resistant mask layout in a full-chip scale. This method includes designing a layout for the mask, extracting a representative pattern, detecting stress weak points in the pattern, verifying them by forming a pattern on a wafer, and making changes to the design rule for the full-chip layout.
- Method for designing a crack-resistant mask layout in a full-chip scale
- Designing a layout for the mask
- Extracting a representative pattern from the layout
- Detecting stress weak points in the pattern
- Verifying the weak points by forming a pattern on a wafer
- Changing the design rule for the full-chip layout
Potential Applications
- Semiconductor manufacturing
- Integrated circuit design
- Mask layout design
Problems Solved
- Cracks in mask layouts
- Weak points in patterns
- Inefficient design methods
Benefits
- Quick and effective mask layout design
- Improved crack resistance
- Enhanced manufacturing process
Original Abstract Submitted
A mask layout design method capable of quickly and effectively designing a crack-resistant mask layout in a full-chip scale, a mask manufacturing method including the mask layout design method, and a mask layout are provided. The mask layout design method includes designing a full-chip layout with respect to a mask; extracting a representative pattern from the full-chip layout; detecting a stress weak point in the representative pattern; verifying the stress weak point by forming a pattern on a wafer; and changing a design rule with respect to the full-chip layout.
