17949904. BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES simplified abstract (Intel Corporation)
Contents
- 1 BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES
Organization Name
Inventor(s)
Timothy Bauer of Hillsboro OR (US)
James Valerio of North Plains OR (US)
BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17949904 titled 'BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES
Simplified Explanation
Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.
- Technique for decomposing 64-bit per-lane virtual addresses
- Access a plurality of data elements on a multi-lane parallel processing execution resource
- Decomposition into base address and per-lane offsets
- Memory access circuitry reconstructs per-lane addresses
Potential Applications
This technology could be applied in:
- Graphics processing units
- Compute accelerators
- High-performance computing systems
Problems Solved
- Efficient access to multiple data elements in parallel processing
- Optimized memory access for graphics and compute tasks
Benefits
- Improved performance in parallel processing tasks
- Enhanced memory access efficiency
- Increased overall system speed and throughput
Potential Commercial Applications
Optimized Memory Access Technique for Multi-Lane Parallel Processing Execution Resources
Possible Prior Art
No prior art known at this time.
Unanswered Questions
How does this technique compare to existing methods for memory access in parallel processing systems?
The article does not provide a direct comparison with existing methods for memory access in parallel processing systems.
What specific types of data elements can be efficiently accessed using this technique?
The article does not specify the types of data elements that can be efficiently accessed using this technique.
Original Abstract Submitted
Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.
