17949732. POWER VIA RESONANCE SUPPRESSION simplified abstract (HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP)

POWER VIA RESONANCE SUPPRESSION

Organization Name

HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor(s)

Melvin Kent Benedict of Magnolia TX (US)

Chi Kim Sides of Spring TX (US)

Paul Danna of Pearland TX (US)

Michael Chan of Bellaire TX (US)

POWER VIA RESONANCE SUPPRESSION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17949732 titled 'POWER VIA RESONANCE SUPPRESSION

Simplified Explanation

The patent application describes a printed circuit board (PCB) with multiple layers and plated through-hole vias for power distribution.

• The PCB includes a top layer for mounting components, a second surface layer, and a first power layer for power distribution.
• Plated through-hole vias connect the layers, with power vias providing power to components on the top layer.
• The stub length of the power via is shorter than the distance between the power layer and the second surface layer, optimizing power distribution efficiency.

Potential Applications

The technology described in this patent application could be applied in various electronic devices and systems that require efficient power distribution, such as smartphones, laptops, and IoT devices.

Problems Solved

This technology solves the problem of inefficient power distribution in multi-layer PCBs, ensuring that components receive power effectively without signal interference or power loss.

Benefits

The benefits of this technology include improved power distribution efficiency, reduced signal interference, and enhanced overall performance of electronic devices.

Potential Commercial Applications

The technology could be utilized in the consumer electronics industry, telecommunications sector, and automotive industry for the development of advanced electronic devices with optimized power distribution capabilities.

Possible Prior Art

One possible prior art in this field is the use of blind and buried vias in multi-layer PCBs to improve signal integrity and reduce signal interference. However, the specific optimization of power vias for efficient power distribution as described in this patent application may be a novel approach.

How does this technology compare to existing power distribution methods in multi-layer PCBs?

This article does not provide a direct comparison with existing power distribution methods in multi-layer PCBs. Further research and testing would be needed to evaluate the performance and efficiency of this technology in comparison to traditional methods.

What are the potential challenges in implementing this technology in mass production of electronic devices?

The article does not address the potential challenges in mass production, such as cost implications, manufacturing complexity, and compatibility with existing production processes. Further analysis and testing would be required to assess the feasibility of large-scale implementation.

Original Abstract Submitted

One aspect provides a printed circuit board (PCB). The PCB can include a plurality of layers and a plurality of plated through-hole (PTH) vias extending through the plurality of layers. The plurality of layers can include at least a top layer for mounting components, a second surface layer, and a first power layer positioned between the top layer and the second surface layer. The plurality of PTH vias can include at least one power via coupled to the first power layer to provide power to components mounted on the top layer. A stub length of the power via can be less than a distance between the power layer and the second surface layer.