17947071. FERRORELECTRIC FIELD-EFFECT TRANSISTOR (FEFET) DEVICES WITH LOW OPERATING VOLTAGE CAPABILITIES simplified abstract (Intel Corporation)
Contents
- 1 FERRORELECTRIC FIELD-EFFECT TRANSISTOR (FEFET) DEVICES WITH LOW OPERATING VOLTAGE CAPABILITIES
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 FERRORELECTRIC FIELD-EFFECT TRANSISTOR (FEFET) DEVICES WITH LOW OPERATING VOLTAGE CAPABILITIES - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
FERRORELECTRIC FIELD-EFFECT TRANSISTOR (FEFET) DEVICES WITH LOW OPERATING VOLTAGE CAPABILITIES
Organization Name
Inventor(s)
Punyashloka Debashis of Hillsboro OR (US)
Rachel A. Steinhardt of Beaverton OR (US)
Brandon Holybee of Portland OR (US)
Kevin P. O'brien of Portland OR (US)
Dmitri Evgenievich Nikonov of Beaverton OR (US)
John J. Plombon of Portland OR (US)
Ian Alexander Young of Olympia WA (US)
Raseong Kim of Portland OR (US)
Carly Rogan of North Plains OR (US)
Dominique A. Adams of Portland OR (US)
Arnab Sen Gupta of Hillsboro OR (US)
Marko Radosavljevic of Portland OR (US)
Scott B. Clendenning of Portland OR (US)
Gauri Auluck of Hillsboro OR (US)
Matthew V. Metz of Portland OR (US)
Tristan A. Tronic of Aloha OR (US)
I-Cheng Tung of Hillsboro OR (US)
FERRORELECTRIC FIELD-EFFECT TRANSISTOR (FEFET) DEVICES WITH LOW OPERATING VOLTAGE CAPABILITIES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17947071 titled 'FERRORELECTRIC FIELD-EFFECT TRANSISTOR (FEFET) DEVICES WITH LOW OPERATING VOLTAGE CAPABILITIES
Simplified Explanation
The abstract describes a transistor device with specific layers and materials arranged in a particular configuration.
- The transistor device includes a gate material layer, a ferroelectric (FE) material layer, a semiconductor channel material layer, and first and second source/drain materials.
- The FE material layer is positioned between the gate material and the source/drain materials.
- The first source/drain material is adjacent to the semiconductor channel material layer, while the second source/drain material is on the opposite side of the channel material layer.
- The FE material layer is divided into two portions, with each portion directly between the gate material and one of the source/drain materials.
Potential Applications
This technology could be applied in:
- Advanced electronic devices
- Memory storage devices
- High-performance computing systems
Problems Solved
This technology helps in:
- Improving transistor performance
- Enhancing data storage capabilities
- Increasing energy efficiency in electronic devices
Benefits
The benefits of this technology include:
- Faster data processing speeds
- Higher memory density
- Lower power consumption in electronic devices
Potential Commercial Applications
The potential commercial applications of this technology could be in:
- Semiconductor industry
- Electronics manufacturing sector
- Research and development organizations
Possible Prior Art
One possible prior art for this technology could be:
- Previous patents related to ferroelectric materials in transistor devices
Unanswered Questions
How does this technology compare to existing transistor designs?
This article does not provide a direct comparison to existing transistor designs in terms of performance, efficiency, or cost.
What are the specific manufacturing processes involved in creating this transistor device?
The article does not detail the specific steps or techniques used in manufacturing this transistor device.
Original Abstract Submitted
In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.
- Intel Corporation
- Punyashloka Debashis of Hillsboro OR (US)
- Rachel A. Steinhardt of Beaverton OR (US)
- Brandon Holybee of Portland OR (US)
- Kevin P. O'brien of Portland OR (US)
- Dmitri Evgenievich Nikonov of Beaverton OR (US)
- John J. Plombon of Portland OR (US)
- Ian Alexander Young of Olympia WA (US)
- Raseong Kim of Portland OR (US)
- Carly Rogan of North Plains OR (US)
- Dominique A. Adams of Portland OR (US)
- Arnab Sen Gupta of Hillsboro OR (US)
- Marko Radosavljevic of Portland OR (US)
- Scott B. Clendenning of Portland OR (US)
- Gauri Auluck of Hillsboro OR (US)
- Hai Li of Portland OR (US)
- Matthew V. Metz of Portland OR (US)
- Tristan A. Tronic of Aloha OR (US)
- I-Cheng Tung of Hillsboro OR (US)
- H01L29/78
- H01L29/51