17946541. BLOCK LAYER PERSISTENT MEMORY BUFFER simplified abstract (Western Digital Technologies, Inc.)
Contents
- 1 BLOCK LAYER PERSISTENT MEMORY BUFFER
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 BLOCK LAYER PERSISTENT MEMORY BUFFER - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
BLOCK LAYER PERSISTENT MEMORY BUFFER
Organization Name
Western Digital Technologies, Inc.
Inventor(s)
Shay Benisty of Beer Sheva (IL)
Judah Gamliel Hahn of Ofra (IL)
BLOCK LAYER PERSISTENT MEMORY BUFFER - A simplified explanation of the abstract
This abstract first appeared for US patent application 17946541 titled 'BLOCK LAYER PERSISTENT MEMORY BUFFER
Simplified Explanation
The present disclosure relates to improved access to DRAM using namespace mapping, where the PMR address range is mapped to LBA address space. This allows the host to access the PMR indirectly using NVMe commands, potentially leading to higher performance and lower latency.
- PMR address range mapped to LBA address space
- Host can access PMR indirectly using NVMe commands
- Implementation of Power Loss Protection (PLP) feature over PMR
- Internal SRAMs mapped in LBA address space for debug purposes
- Internal flops holding important data also mapped in LBA address space
Potential Applications
This technology could be applied in data storage systems, high-performance computing, and server applications where fast and efficient access to data is crucial.
Problems Solved
This technology solves the problem of improving access to DRAM and optimizing data storage and retrieval processes in high-performance computing systems.
Benefits
The benefits of this technology include faster access to data, lower latency, improved performance, and enhanced reliability through the implementation of the Power Loss Protection feature.
Potential Commercial Applications
Potential commercial applications of this technology include data centers, cloud computing providers, and any industry requiring high-speed data storage and retrieval capabilities.
Possible Prior Art
One possible prior art could be the use of namespace mapping in storage systems to optimize data access and improve performance.
Unanswered Questions
How does this technology compare to existing solutions in terms of performance and reliability?
This article does not provide a direct comparison with existing solutions in terms of performance and reliability. Further research or testing may be needed to determine the specific advantages of this technology over others.
What are the potential limitations or drawbacks of implementing this technology in practical applications?
The article does not address potential limitations or drawbacks of implementing this technology in practical applications. Factors such as cost, compatibility with existing systems, and scalability could be important considerations that are not covered in the abstract.
Original Abstract Submitted
The present disclosure generally relates to improved access to the DRAM using namespace mapping. The PMR address range is mapped to LBA address space. Mapping the PMR address range in LBA address space allows the host to access the PMR indirectly using NVMe commands. The host device may hold in the namespace the most frequently accessed data and obtain highest performance and low latency. Implementation of the Power Loss Protection (PLP) feature over the PMR makes the system prefer storing the data in PMR rather in host memory. All internal SRAMs (e.g. Transfer RAMs, XOR RAMs, etc.) may be mapped in the LBA address space so the host device can access mainly for debug purposes. Some internal flops that hold important data are mapped in the LBA address space as well.
